Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7782080 | High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devices | — | 2010-08-24 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM | Jon Allan Faue, Michael A. Murray | 2008-03-25 |
| 7071745 | Voltage-controlled analog delay locked loop | John D. Heightley | 2006-07-04 |
| 7061823 | Limited output address register technique providing selectively variable write latency in DDR2 (double data rate two) integrated circuit memory devices | Jon Allan Faue | 2006-06-13 |
| 7054215 | Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage | Kook-Hwan Kwon | 2006-05-30 |
| 7016235 | Data sorting in memories | Jon Allan Faue | 2006-03-21 |
| 6721224 | Memory refresh methods and circuits | Michael A. Murray, Li-Chun Li | 2004-04-13 |