| 7876137 |
Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices |
— |
2011-01-25 |
| 7518425 |
Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices |
— |
2009-04-14 |
| 7474136 |
Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device |
— |
2009-01-06 |
| 7218564 |
Dual equalization devices for long data line pairs |
Jon Allan Faue |
2007-05-15 |
| 7167052 |
Low voltage differential amplifier circuit for wide voltage range operation |
Jon Allan Faue |
2007-01-23 |
| 7102439 |
Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels |
Jon Allan Faue |
2006-09-05 |
| 7071745 |
Voltage-controlled analog delay locked loop |
Steve Eaton |
2006-07-04 |
| 7061322 |
Low voltage differential amplifier circuit and bias control technique enabling accommodation of an increased range of input levels |
— |
2006-06-13 |
| 6741488 |
Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device |
Jon Allan Faue |
2004-05-25 |
| 6469559 |
System and method for eliminating pulse width variations in digital delay lines |
— |
2002-10-22 |
| 6445621 |
Dynamic data amplifier with built-in voltage level shifting |
— |
2002-09-03 |
| 6434069 |
Two-phase charge-sharing data latch for memory circuit |
Kim C. Hardee |
2002-08-13 |
| 6415374 |
System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM) |
Jon Allan Faue |
2002-07-02 |
| 6359487 |
System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line |
Jon Allan Faue |
2002-03-19 |
| 6339354 |
System and method for eliminating pulse width variations in digital delay lines |
— |
2002-01-15 |
| 6339541 |
Architecture for high speed memory circuit having a relatively large number of internal data lines |
Kim C. Hardee, Lawrence Lee Aldrich |
2002-01-15 |
| 4363111 |
Dummy cell arrangement for an MOS memory |
Sargent S. Eaton, Jr. |
1982-12-07 |
| 4355377 |
Asynchronously equillibrated and pre-charged static ram |
Rahul Sud, Kim C. Hardee |
1982-10-19 |