Issued Patents All Time
Showing 1–25 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10103731 | Calibration circuit for on-chip drive and on-die termination | — | 2018-10-16 |
| 9780785 | Calibration circuit for on-chip drive and on-die termination | — | 2017-10-03 |
| 8339882 | Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM | Michael C. Parris | 2012-12-25 |
| 7649406 | Short-circuit charge-sharing technique for integrated circuit devices | Michael C. Parris | 2010-01-19 |
| 7609570 | Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values | Michael C. Parris, Douglas Butler | 2009-10-27 |
| 7606093 | Optimized charge sharing for data bus skew applications | Michael C. Parris | 2009-10-20 |
| 7506100 | Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks | Douglas Butler, Oscar Frederick Jones, Jr., Michael C. Parris | 2009-03-17 |
| 7463054 | Data bus charge-sharing technique for integrated circuit devices | Michael C. Parris | 2008-12-09 |
| 7372765 | Power-gating system and method for integrated circuit devices | — | 2008-05-13 |
| 7359277 | High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation | — | 2008-04-15 |
| 7248522 | Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM) | — | 2007-07-24 |
| 7180363 | Powergating method and apparatus | Michael C. Parris | 2007-02-20 |
| 7154795 | Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM | Michael C. Parris | 2006-12-26 |
| 7151711 | Self-addressed subarray precharge | — | 2006-12-19 |
| RE39274 | Voltage down converter with switched hysteresis | — | 2006-09-12 |
| 7053692 | Powergate control using boosted and negative voltages | Michael C. Parris | 2006-05-30 |
| 6990029 | Column read amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM) | — | 2006-01-24 |
| 6912168 | Non-contiguous masked refresh for an integrated circuit memory | Michael C. Parris, Douglas Butler, Oscar Frederick Jones, Jr. | 2005-06-28 |
| 6788590 | Bitline reference voltage circuit | Michael C. Parris | 2004-09-07 |
| 6738302 | Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays | Michael C. Parris | 2004-05-18 |
| 6731156 | High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages | Michael C. Parris | 2004-05-04 |
| 6643160 | Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements | — | 2003-11-04 |
| 6625069 | Data path decoding technique for an embedded memory array | Michael C. Parris | 2003-09-23 |
| 6625078 | Look-ahead refresh for an integrated circuit memory | Oscar Frederick Jones, Jr. | 2003-09-23 |
| 6625066 | Data path decoding technique for an embedded memory array | Michael C. Parris | 2003-09-23 |