Issued Patents All Time
Showing 26–50 of 79 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6608797 | Automatic delay technique for early read and write operations in synchronous dynamic random access memories | Michael C. Parris, Oscar Frederick Jones, Jr. | 2003-08-19 |
| 6597201 | Dynamic predecoder circuitry for memory circuits | Michael C. Parris | 2003-07-22 |
| 6580306 | Switching circuit utilizing a high voltage transistor protection technique for integrated circuit devices incorporating dual supply voltage sources | — | 2003-06-17 |
| 6552943 | Sense amplifier for dynamic random access memory (“DRAM”) devices having enhanced read and write speed | — | 2003-04-22 |
| 6549470 | Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays | Michael C. Parris | 2003-04-15 |
| 6531900 | Negative voltage driver circuit technique having reduced current flow to the negative supply voltage source | — | 2003-03-11 |
| 6515926 | Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time | Michael C. Parris | 2003-02-04 |
| 6501817 | Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance | Michael C. Parris | 2002-12-31 |
| 6458644 | Data bus architecture for integrated circuit devices having embedded dynamic random access memory (DRAM) with a large aspect ratio providing reduced capacitance and power requirements | — | 2002-10-01 |
| 6434069 | Two-phase charge-sharing data latch for memory circuit | John D. Heightley | 2002-08-13 |
| 6414897 | Local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (DRAM) | Michael C. Parris | 2002-07-02 |
| 6339541 | Architecture for high speed memory circuit having a relatively large number of internal data lines | John D. Heightley, Lawrence Lee Aldrich | 2002-01-15 |
| 6300810 | Voltage down converter with switched hysteresis | — | 2001-10-09 |
| 6285242 | Reference voltage shifter | — | 2001-09-04 |
| 6278653 | Reduced skew timing scheme for write circuitry used in memory circuits | — | 2001-08-21 |
| 6275432 | Method of reading and writing data using local data read and local data write circuits | — | 2001-08-14 |
| 6266266 | Integrated circuit design exhibiting reduced capacitance | Lawrence Lee Aldrich | 2001-07-24 |
| 6262935 | Shift redundancy scheme for wordlines in memory circuits | Michael C. Parris | 2001-07-17 |
| 6249469 | Sense amplifier with local sense drivers and local read amplifiers | — | 2001-06-19 |
| 6208574 | Sense amplifier with local column read amplifier and local data write drivers | — | 2001-03-27 |
| 6195302 | Dual slope sense clock generator | — | 2001-02-27 |
| 6088270 | Sense amplifier with local write drivers | — | 2000-07-11 |
| 6031407 | Low power circuit for detecting a slow changing input | Michael V. Cordoba | 2000-02-29 |
| 5680362 | Circuit and method for accessing memory cells of a memory device | Michael C. Parris, Douglas Butler | 1997-10-21 |
| 5570005 | Wide range power supply for integrated circuits | Michael V. Cordoba | 1996-10-29 |