Issued Patents All Time
Showing 1–25 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9558808 | DRAM security erase | — | 2017-01-31 |
| 9557364 | System and method for testing fuse blow reliability for integrated circuits | — | 2017-01-31 |
| 9299417 | DRAM security erase | — | 2016-03-29 |
| 9230814 | Non-volatile memory devices having vertical drain to gate capacitive coupling | David Edward Fisch | 2016-01-05 |
| 9158352 | Power boosting circuit for semiconductor packaging | Richard Dewitt Crisp, Mark Kroot | 2015-10-13 |
| 8976572 | DRAM security erase | — | 2015-03-10 |
| 8970003 | Embedded passive integration | — | 2015-03-03 |
| 8873302 | Common doped region with separate gate control for a logic compatible non-volatile memory cell | David Edward Fisch, William C. Plants | 2014-10-28 |
| 8736278 | System and method for testing fuse blow reliability for integrated circuits | — | 2014-05-27 |
| 8699263 | DRAM security erase | — | 2014-04-15 |
| 8692611 | Power boosting circuit for semiconductor packaging | Richard Dewitt Crisp, Mark Kroot | 2014-04-08 |
| RE44726 | Data inversion register technique for integrated circuit memory testing | Oscar Frederick Jones, Jr. | 2014-01-21 |
| 8339882 | Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM | Kim C. Hardee | 2012-12-25 |
| 8281219 | Error correction code (ECC) circuit test mode | Oscar Frederick Jones, Jr. | 2012-10-02 |
| 7916567 | Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM | Douglas Butler | 2011-03-29 |
| 7649406 | Short-circuit charge-sharing technique for integrated circuit devices | Kim C. Hardee | 2010-01-19 |
| 7631233 | Data inversion register technique for integrated circuit memory testing | Oscar Frederick Jones, Jr. | 2009-12-08 |
| 7609570 | Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values | Douglas Butler, Kim C. Hardee | 2009-10-27 |
| 7606093 | Optimized charge sharing for data bus skew applications | Kim C. Hardee | 2009-10-20 |
| 7586355 | Low skew clock distribution tree | Oscar Frederick Jones, Jr. | 2009-09-08 |
| 7580304 | Multiple bus charge sharing | — | 2009-08-25 |
| 7506100 | Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks | Douglas Butler, Oscar Frederick Jones, Jr., Kim C. Hardee | 2009-03-17 |
| 7463054 | Data bus charge-sharing technique for integrated circuit devices | Kim C. Hardee | 2008-12-09 |
| 7298171 | Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices | — | 2007-11-20 |
| 7180363 | Powergating method and apparatus | Kim C. Hardee | 2007-02-20 |