Issued Patents All Time
Showing 25 most recent of 111 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362182 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, David Edward Fisch | 2025-07-15 |
| 11823906 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, David Edward Fisch | 2023-11-21 |
| 11289333 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, David Edward Fisch | 2022-03-29 |
| 10832912 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, David Edward Fisch | 2020-11-10 |
| 10684929 | Self healing compute array | Javier A. Delacruz, Steven Teig, David Edward Fisch | 2020-06-16 |
| 10522352 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, David Edward Fisch | 2019-12-31 |
| 10409677 | Enhanced memory reliability in stacked memory devices | — | 2019-09-10 |
| 10295588 | Wafer testing without direct probing | Javier A. Delacruz | 2019-05-21 |
| 10262717 | DRAM adjacent row disturb mitigation | David Edward Fisch | 2019-04-16 |
| 10169143 | Preferred state encoding in non-volatile memories | — | 2019-01-01 |
| 10083079 | Enhanced memory reliability in stacked memory devices | — | 2018-09-25 |
| 10020811 | FPGA RAM blocks optimized for use as register files | Joel Landry, Jonathan W. Greene, Wenyi Feng | 2018-07-10 |
| 10007573 | Preferred state encoding in non-volatile memories | — | 2018-06-26 |
| 9812185 | DRAM adjacent row disturb mitigation | David Edward Fisch | 2017-11-07 |
| 9780792 | FPGA RAM blocks optimized for use as register files | Joel Landry, Jonathan W. Greene, Wenyi Feng | 2017-10-03 |
| 9778984 | Enhanced memory reliability in stacked memory devices | — | 2017-10-03 |
| 9548101 | Retention optimized memory device using predictive data inversion | David Edward Fisch, Kent Stalnaker | 2017-01-17 |
| 9299398 | Retention optimized memory device using predictive data inversion | David Edward Fisch, Kent Stalnaker | 2016-03-29 |
| 9007866 | Retention optimized memory device using predictive data inversion | David Edward Fisch, Kent Stalnaker | 2015-04-14 |
| 8873302 | Common doped region with separate gate control for a logic compatible non-volatile memory cell | David Edward Fisch, Michael C. Parris | 2014-10-28 |
| 8446170 | FPGA RAM blocks optimized for use as register files | Joel Landry, Jonathan W. Greene, Wenyi Feng | 2013-05-21 |
| 8258811 | Enhanced field programmable gate array | Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan | 2012-09-04 |
| 8067959 | Programmable delay line compensated for process, voltage, and temperature | Suhail Zain, Joel Landry, Gregory Bakker, Tomek P. Jasinoski | 2011-11-29 |
| 7977970 | Enhanced field programmable gate array | Samuel W. Beal, Sinan Kaptanoglu, Jung-Cheun Lien, William Shu, King W. Chan | 2011-07-12 |
| 7956404 | Non-volatile two-transistor programmable logic cell and array layout | Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, Zhigang Wang | 2011-06-07 |