Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362182 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, William C. Plants | 2025-07-15 |
| 12293108 | 3D memory circuit | Javier A. Delacruz | 2025-05-06 |
| 12272730 | Transistor level interconnection methodologies utilizing 3D interconnects | Javier A. Delacruz | 2025-04-08 |
| 12113054 | Non-volatile dynamic random access memory | Javier A. Delacruz, Pearl Po-Yee Cheng | 2024-10-08 |
| 11977211 | Multi-modal wide-angle illumination employing a compound beam combiner | Avraham Adler, Ilia Lutsker, Yigal Katzir, Avinoam Rosenberg | 2024-05-07 |
| 11823906 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, William C. Plants | 2023-11-21 |
| 11688776 | Transistor level interconnection methodologies utilizing 3D interconnects | Javier A. Delacruz | 2023-06-27 |
| 11599299 | 3D memory circuit | Javier A. Delacruz | 2023-03-07 |
| 11398258 | Multi-die module with low power operation | — | 2022-07-26 |
| 11289333 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, William C. Plants | 2022-03-29 |
| 11127738 | Back biasing of FD-SOI circuit blocks | Javier A. Delacruz, Kenneth Duong, Xu Chang, Liang Wang | 2021-09-21 |
| 10991804 | Transistor level interconnection methodologies utilizing 3D interconnects | Javier A. Delacruz | 2021-04-27 |
| 10832912 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, William C. Plants | 2020-11-10 |
| 10684929 | Self healing compute array | Javier A. Delacruz, Steven Teig, William C. Plants | 2020-06-16 |
| 10522352 | Direct-bonded native interconnects and active base die | Javier A. Delacruz, Steven Teig, Shaowu Huang, William C. Plants | 2019-12-31 |
| 10455137 | Auto-focus system | Ofer Saphier, Doron Malka | 2019-10-22 |
| 10262717 | DRAM adjacent row disturb mitigation | William C. Plants | 2019-04-16 |
| 10164633 | On-chip impedance network with digital coarse and analog fine tuning | Curtis J. Dicke, George Courville, Randall L. Sandusky, Kent Stalnaker | 2018-12-25 |
| 9812185 | DRAM adjacent row disturb mitigation | William C. Plants | 2017-11-07 |
| 9712600 | Transmission of notifications for retrieving an application on a mobile client device | Teck Chia, Jordan Alperin, Vijaye Ganesh Raji | 2017-07-18 |
| 9705497 | On-chip impedance network with digital coarse and analog fine tuning | Curtis J. Dicke, George Courville, Randall L. Sandusky, Kent Stalnaker | 2017-07-11 |
| 9620433 | Packaged microelectronic elements having blind vias for heat dissipation | — | 2017-04-11 |
| 9548101 | Retention optimized memory device using predictive data inversion | William C. Plants, Kent Stalnaker | 2017-01-17 |
| 9299398 | Retention optimized memory device using predictive data inversion | William C. Plants, Kent Stalnaker | 2016-03-29 |
| 9257155 | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same | Philippe Bauser | 2016-02-09 |