Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7161214 | Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays | — | 2007-01-09 |
| 7154795 | Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM | Kim C. Hardee | 2006-12-26 |
| 7110306 | Dual access DRAM | Oscar Frederick Jones, Jr., Douglas Butler | 2006-09-19 |
| 7099234 | Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM | Oscar Frederick Jones, Jr., Douglas Butler | 2006-08-29 |
| 7053692 | Powergate control using boosted and negative voltages | Kim C. Hardee | 2006-05-30 |
| 7002874 | Dual word line mode for DRAMs | Douglas Butler, Oscar Frederick Jones, Jr. | 2006-02-21 |
| 6912168 | Non-contiguous masked refresh for an integrated circuit memory | Douglas Butler, Kim C. Hardee, Oscar Frederick Jones, Jr. | 2005-06-28 |
| 6788590 | Bitline reference voltage circuit | Kim C. Hardee | 2004-09-07 |
| 6744690 | Asynchronous input data path technique for increasing speed and reducing latency in integrated circuit devices incorporating dynamic random access memory (DRAM) arrays and embedded DRAM | — | 2004-06-01 |
| 6738302 | Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays | Kim C. Hardee | 2004-05-18 |
| 6731156 | High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages | Kim C. Hardee | 2004-05-04 |
| 6732305 | Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry | Oscar Frederick Jones, Jr. | 2004-05-04 |
| 6728931 | Time data compression technique for high speed integrated circuit memory devices | Oscar Frederick Jones, Jr. | 2004-04-27 |
| 6657461 | System and method for high speed integrated circuit device testing utilizing a lower speed test environment | Oscar Frederick Jones, Jr. | 2003-12-02 |
| 6643212 | Simultaneous function dynamic random access memory device technique | Oscar Frederick Jones, Jr. | 2003-11-04 |
| 6625066 | Data path decoding technique for an embedded memory array | Kim C. Hardee | 2003-09-23 |
| 6625069 | Data path decoding technique for an embedded memory array | Kim C. Hardee | 2003-09-23 |
| 6608797 | Automatic delay technique for early read and write operations in synchronous dynamic random access memories | Kim C. Hardee, Oscar Frederick Jones, Jr. | 2003-08-19 |
| 6597201 | Dynamic predecoder circuitry for memory circuits | Kim C. Hardee | 2003-07-22 |
| 6570799 | Precharge and reference voltage technique for dynamic random access memories | — | 2003-05-27 |
| 6549470 | Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays | Kim C. Hardee | 2003-04-15 |
| 6515926 | Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time | Kim C. Hardee | 2003-02-04 |
| 6512394 | Technique for efficient logic power gating with data retention in integrated circuit devices | — | 2003-01-28 |
| 6501817 | Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance | Kim C. Hardee | 2002-12-31 |
| 6414897 | Local write driver circuit for an integrated circuit device incorporating embedded dynamic random access memory (DRAM) | Kim C. Hardee | 2002-07-02 |