Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6566720 | Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits | — | 2003-05-20 |
| 6339541 | Architecture for high speed memory circuit having a relatively large number of internal data lines | Kim C. Hardee, John D. Heightley | 2002-01-15 |
| 6266266 | Integrated circuit design exhibiting reduced capacitance | Kim C. Hardee | 2001-07-24 |