Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9977485 | Cache array with reduced power consumption | Paul A. Bunce, John D. Davis, Jigar Vora | 2018-05-22 |
| 9971394 | Cache array with reduced power consumption | Paul A. Bunce, John D. Davis, Jigar Vora | 2018-05-15 |
| 9355692 | High frequency write through memory device | Paul A. Bunce, Yuen H. Chan, John D. Davis, Jigar Vora | 2016-05-31 |
| 9281024 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, Yuen H. Chan, John D. Davis | 2016-03-08 |
| 9281025 | Write/read priority blocking scheme using parallel static address decode path | Paul A. Bunce, Yuen H. Chan, John D. Davis | 2016-03-08 |
| 9070433 | SRAM supply voltage global bitline precharge pulse | Paul A. Bunce, Yuen H. Chan, John D. Davis | 2015-06-30 |
| 8861284 | Increasing memory operating frequency | Paul A. Bunce, John D. Davis, Jigar Vora | 2014-10-14 |
| 8599642 | Port enable signal generation for gating a memory array device output | Paul A. Bunce, John D. Davis, Jigar Vora | 2013-12-03 |
| 8351278 | Jam latch for latching memory array output data | Paul A. Bunce, John D. Davis, Jigar Vora | 2013-01-08 |
| 8345490 | Split voltage level restore and evaluate clock signals for memory address decoding | Paul A. Bunce, John D. Davis, Jigar Vora | 2013-01-01 |
| 8345497 | Internal bypassing of memory array devices | Paul A. Bunce, John D. Davis, Jigar Vora | 2013-01-01 |