Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11150818 | Memory array having power consumption characteristics | Russell Hayes, Brian James Yavoich, John D. Davis | 2021-10-19 |
| 11067627 | Noise injection circuit | Brian James Yavoich, John D. Davis, Russell Hayes | 2021-07-20 |
| 10978140 | Random-access memory array memory cell selection | John D. Davis, Brian James Yavoich, Russell Hayes | 2021-04-13 |
| 10840895 | Fine-grained programmable delay and pulse shaping circuit | John D. Davis, Brian James Yavoich, Russell Hayes | 2020-11-17 |
| 10367507 | Dynamic decode circuit with active glitch control | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2019-07-30 |
| 10320388 | Dynamic decode circuit with active glitch control method | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2019-06-11 |
| 10312915 | Dynamic decode circuit with active glitch control method | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2019-06-04 |
| 10312916 | Dynamic decode circuit with delayed precharge | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2019-06-04 |
| 10224933 | Dynamic decode circuit with active glitch control | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2019-03-05 |
| 9997218 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2018-06-12 |
| 9977485 | Cache array with reduced power consumption | John D. Davis, Diana M. Henderson, Jigar Vora | 2018-05-22 |
| 9971394 | Cache array with reduced power consumption | John D. Davis, Diana M. Henderson, Jigar Vora | 2018-05-15 |
| 9966958 | Dynamic decode circuit with active glitch control | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2018-05-08 |
| 9792967 | Managing semiconductor memory array leakage current | Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-17 |
| 9786339 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-10-10 |
| 9761289 | Managing semiconductor memory array leakage current | Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt, Tobias Werner +1 more | 2017-09-12 |
| 9742408 | Dynamic decode circuit with active glitch control | Yuen H. Chan, John D. Davis, Antonio R. Pelella | 2017-08-22 |
| 9583211 | Incorporating bit write capability with column interleave write enable and column redundancy steering | John D. Davis, Russell Hayes, Brian James Yavoich | 2017-02-28 |
| 9355692 | High frequency write through memory device | Yuen H. Chan, John D. Davis, Diana M. Henderson, Jigar Vora | 2016-05-31 |
| 9281025 | Write/read priority blocking scheme using parallel static address decode path | Yuen H. Chan, John D. Davis, Diana M. Henderson | 2016-03-08 |
| 9281024 | Write/read priority blocking scheme using parallel static address decode path | Yuen H. Chan, John D. Davis, Diana M. Henderson | 2016-03-08 |
| 9070433 | SRAM supply voltage global bitline precharge pulse | Yuen H. Chan, John D. Davis, Diana M. Henderson | 2015-06-30 |
| 8861284 | Increasing memory operating frequency | John D. Davis, Diana M. Henderson, Jigar Vora | 2014-10-14 |
| 8599642 | Port enable signal generation for gating a memory array device output | John D. Davis, Diana M. Henderson, Jigar Vora | 2013-12-03 |
| 8351278 | Jam latch for latching memory array output data | John D. Davis, Diana M. Henderson, Jigar Vora | 2013-01-08 |