Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8345490 | Split voltage level restore and evaluate clock signals for memory address decoding | John D. Davis, Diana M. Henderson, Jigar Vora | 2013-01-01 |
| 8345497 | Internal bypassing of memory array devices | John D. Davis, Diana M. Henderson, Jigar Vora | 2013-01-01 |
| 8299833 | Programmable control clock circuit including scan mode | Yuen H. Chan, John D. Davis, Richard Edward Serton | 2012-10-30 |
| 7688650 | Write control method for a memory array configured with multiple memory subarrays | John D. Davis, Donald W. Plass, Kenneth J. Reyer | 2010-03-30 |
| 7471590 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Donald W. Plass, Kenneth J. Reyer | 2008-12-30 |
| 7299374 | Clock control method and apparatus for a memory array | James Dawson, Donald W. Plass, Kenneth J. Reyer | 2007-11-20 |
| 7283417 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Donald W. Plass, Kenneth J. Reyer | 2007-10-16 |
| 7266737 | Method for enabling scan of defective ram prior to repair | John D. Davis, Patrick J. Meaney, Donald W. Plass | 2007-09-04 |
| 7233542 | Method and apparatus for address generation | John D. Davis, Donald W. Plass | 2007-06-19 |
| 7210084 | Integrated system logic and ABIST data compression for an SRAM directory | John D. Davis, Thomas J. Knips, Donald W. Plass | 2007-04-24 |
| 7102944 | Programmable analog control of a bitline evaluation circuit | John D. Davis, Donald W. Plass | 2006-09-05 |
| 7099203 | Circuit and method for writing a binary value to a memory cell | John D. Davis, Donald W. Plass | 2006-08-29 |
| 7088638 | Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays | John D. Davis, James Dawson, Donald W. Plass | 2006-08-08 |
| 7085173 | Write driver circuit for memory array | John D. Davis, Donald W. Plass | 2006-08-01 |
| 7075855 | Memory output timing control circuit with merged functions | John D. Davis, Donald W. Plass | 2006-07-11 |
| 7023759 | System and method for synchronizing memory array signals | John D. Davis, Donald W. Plass | 2006-04-04 |
| 7009895 | Method for skip over redundancy decode with very low overhead | John D. Davis, Thomas J. Knips, Donald W. Plass | 2006-03-07 |
| 6822885 | High speed latch and compare function | John D. Davis, Donald W. Plass | 2004-11-23 |
| 6728912 | SOI cell stability test method | James Dawson, Donald W. Plass | 2004-04-27 |
| 6584023 | System for implementing a column redundancy scheme for arrays with controls that span multiple data bits | John D. Davis, Thomas J. Knips, Donald W. Plass | 2003-06-24 |