Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10943647 | Bit-line mux driver with diode header for computer memory | Gregory J. Fredeman, Thomas E. Miller, Dinesh Kannambadi, Donald W. Plass | 2021-03-09 |
| 10930339 | Voltage bitline high (VBLH) regulation for computer memory | Gregory J. Fredeman, Bishan He, Dinesh Kannambadi, Donald W. Plass | 2021-02-23 |
| 9748958 | Dynamic high voltage driver with adjustable clamped output level | Gregory J. Fredeman, Abraham Mathews, Donald W. Plass | 2017-08-29 |
| 9224437 | Gated-feedback sense amplifier for single-ended local bit-line memories | John E. Barth, Jr., Abraham Mathews, Donald W. Plass | 2015-12-29 |
| 9053770 | Dynamic cascode-managed high-voltage word-line driver circuit | Gregory J. Fredeman, Abraham Mathews, Donald W. Plass | 2015-06-09 |
| 9025403 | Dynamic cascode-managed high-voltage word-line driver circuit | Gregory J. Fredeman, Abraham Mathews, Donald W. Plass | 2015-05-05 |
| 7688650 | Write control method for a memory array configured with multiple memory subarrays | John D. Davis, Paul A. Bunce, Donald W. Plass | 2010-03-30 |
| 7471590 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Paul A. Bunce, Donald W. Plass | 2008-12-30 |
| 7380191 | ABIST data compression and serialization for memory built-in self test of SRAM with redundancy | James Dawson, Thomas J. Knips, Donald W. Plass | 2008-05-27 |
| 7299374 | Clock control method and apparatus for a memory array | James Dawson, Paul A. Bunce, Donald W. Plass | 2007-11-20 |
| 7283417 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Paul A. Bunce, Donald W. Plass | 2007-10-16 |
| 7176725 | Fast pulse powered NOR decode apparatus for semiconductor devices | James Dawson, Donald W. Plass | 2007-02-13 |
| 7170320 | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering | James Dawson, Thomas J. Knips, Donald W. Plass | 2007-01-30 |
| 7099206 | High density bitline selection apparatus for semiconductor memory devices | James Dawson, Donald W. Plass | 2006-08-29 |
| 7068554 | Apparatus and method for implementing multiple memory redundancy with delay tracking clock | James Dawson, Thomas J. Knips, Donald W. Plass | 2006-06-27 |
| 7064990 | Method and apparatus for implementing multiple column redundancy for memory | James Dawson, Thomas J. Knips, Donald W. Plass | 2006-06-20 |