Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11682452 | Local bit select with improved fast read before write suppression | Antonio R. Pelella, Dongho Lee, Genadi Tverskoy, Zhiying Chen | 2023-06-20 |
| 11150818 | Memory array having power consumption characteristics | Russell Hayes, Paul A. Bunce, John D. Davis | 2021-10-19 |
| 11067627 | Noise injection circuit | John D. Davis, Paul A. Bunce, Russell Hayes | 2021-07-20 |
| 10978140 | Random-access memory array memory cell selection | Paul A. Bunce, John D. Davis, Russell Hayes | 2021-04-13 |
| 10840895 | Fine-grained programmable delay and pulse shaping circuit | Paul A. Bunce, John D. Davis, Russell Hayes | 2020-11-17 |
| 9997218 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more | 2018-06-12 |
| 9792967 | Managing semiconductor memory array leakage current | Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more | 2017-10-17 |
| 9786339 | Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation | Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more | 2017-10-10 |
| 9761289 | Managing semiconductor memory array leakage current | Paul A. Bunce, Yuen H. Chan, John D. Davis, Silke Penth, David Edward Schmitt +1 more | 2017-09-12 |
| 9583211 | Incorporating bit write capability with column interleave write enable and column redundancy steering | Paul A. Bunce, John D. Davis, Russell Hayes | 2017-02-28 |