Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9576098 | Lithography aware leakage analysis | Emre Tuncer, Hui Zheng, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2017-02-21 |
| 8572523 | Lithography aware leakage analysis | Emre Tuncer, Hui Zheng, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2013-10-29 |
| 8473876 | Lithography aware timing analysis | Emre Tuncer, Hui Zheng, Anirudh Devgan, Amir Ajami, Alessandra Nardi +3 more | 2013-06-25 |
| 7434188 | Lithographically optimized placement tool | Anirudh Devgan, Roderick Metcalfe, Alfred Wong | 2008-10-07 |
| 6286126 | Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits using best and worst case delay models for nets therein | Brian Zimmerman | 2001-09-04 |
| 5896300 | Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets | Brian Zimmerman | 1999-04-20 |
| 5313398 | Method and apparatus for simulating a microelectronic circuit | Ronald A. Rohrer, J. Eric Bracken | 1994-05-17 |