Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6799308 | Timing analysis of latch-controlled digital circuits with detailed clock skew analysis | Eileen H. You, Matthew Becker, Thomas Dillinger, Micah C. Knapp, Daniel J. Flees +1 more | 2004-09-28 |
| 6662149 | Method and apparatus for efficient computation of moments in interconnect circuits | Anirudh Devgan | 2003-12-09 |
| 6308304 | Method and apparatus for realizable interconnect reduction for on-chip RC circuits | Anirudh Devgan | 2001-10-23 |
| 5796985 | Method and apparatus for incorporating a miller compensation for modeling electrical circuits | Richard P. Wiley | 1998-08-18 |
| 5787008 | Simulation corrected sensitivity | Satyamurthy Pullela, Abhijit Dharchoudhury, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton | 1998-07-28 |