Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7149674 | Methods for analyzing integrated circuits and apparatus therefor | Supamas Sirichotiyakul, David Theodore Blaauw, Timothy J. Edwards, Chanhee OH, Rajendran Panda +2 more | 2006-12-12 |
| 5903471 | Method for optimizing element sizes in a semiconductor device | Satyamurthy Pullela, Timothy J. Edwards, Joseph W. Norton, David Theodore Blaauw | 1999-05-11 |
| 5790415 | Complementary network reduction for load modeling | Satyamurthy Pullela, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton | 1998-08-04 |
| 5787008 | Simulation corrected sensitivity | Satyamurthy Pullela, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton, Peter R. O'Brien | 1998-07-28 |
| 5751593 | Accurate delay prediction based on multi-model analysis | Satyamurthy Pullela, David Theodore Blaauw, Tim J. Edwards, Joseph W. Norton | 1998-05-12 |