Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6799308 | Timing analysis of latch-controlled digital circuits with detailed clock skew analysis | Matthew Becker, Thomas Dillinger, Micah C. Knapp, Daniel J. Flees, Peter R. O'Brien +1 more | 2004-09-28 |
| 6611949 | Path filtering for latch-based systems | Matthew Becker | 2003-08-26 |
| 6526549 | Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits | — | 2003-02-25 |
| 6449754 | Method of measuring the accuracy of parasitic capacitance extraction | Weize Xie, John F. MacDonald | 2002-09-10 |