Issued Patents All Time
Showing 51–75 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7746102 | Bus-based logic blocks for self-timed integrated circuits | Brian C. Gaide | 2010-06-29 |
| 7746101 | Cascading input structure for logic blocks in integrated circuits | — | 2010-06-29 |
| 7743175 | Methods of initializing routing structures in integrated circuits | Ramakrishna K. Tanikella | 2010-06-22 |
| 7733123 | Implementing conditional statements in self-timed logic circuits | Brian C. Gaide | 2010-06-08 |
| 7724016 | Characterizing circuit performance by separating device and interconnect impact on signal delay | Xiao-Jie Yuan, Michael J. Hart, Zicheng Gary Ling | 2010-05-25 |
| 7635989 | Integrated circuits with bus-based programmable interconnect structures | — | 2009-12-22 |
| 7617472 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Suresh M. Menon, Atul V. Ghia +1 more | 2009-11-10 |
| 7605604 | Integrated circuits with novel handshake logic | — | 2009-10-20 |
| 7567997 | Applications of cascading DSP slices | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2009-07-28 |
| 7557610 | Columnar floorplan | — | 2009-07-07 |
| 7548089 | Structures and methods to avoiding hold time violations in a programmable logic device | Trevor J. Bauer, Ramakrishna K. Tanikella | 2009-06-16 |
| 7518401 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon | 2009-04-14 |
| 7499513 | Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit | David E. Tetzlaff, F. Erich Goetting, Marwan Hassoun, Moises E. Robinson | 2009-03-03 |
| 7498192 | Methods of providing a family of related integrated circuits of different sizes | F. Erich Goetting, Trevor J. Bauer, Patrick J. McGuire, Bruce E. Talley, Paul Ying-Fung Wu | 2009-03-03 |
| 7491576 | Yield-enhancing methods of providing a family of scaled integrated circuits | Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh +3 more | 2009-02-17 |
| 7489152 | Characterizing circuit performance by separating device and interconnect impact on signal delay | Xiao-Jie Yuan, Michael J. Hart, Zicheng Gary Ling | 2009-02-10 |
| 7480690 | Arithmetic circuit with multiplexed addend inputs | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2009-01-20 |
| 7478359 | Formation of columnar application specific circuitry using a columnar programmable logic device | Trevor J. Bauer | 2009-01-13 |
| 7472155 | Programmable logic device with cascading DSP slices | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2008-12-30 |
| 7467175 | Programmable logic device with pipelined DSP slices | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2008-12-16 |
| 7467177 | Mathematical circuit with dynamic rounding | James M. Simkins, Jennifer Wong, Bernard J. New, Alvin Y. Ching | 2008-12-16 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi +3 more | 2008-11-18 |
| 7451421 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies | Trevor J. Bauer, Jeffrey V. Lindholm, F. Erich Goetting, Bruce E. Talley, Ramakrishna K. Tanikella | 2008-11-11 |
| 7426678 | Error checking parity and syndrome of a block of data with relocated parity bits | Warren E. Cory, David P. Schultz | 2008-09-16 |
| 7420392 | Programmable gate array and embedded circuitry initialization and processing | David P. Schultz, Stephen M. Douglass, Nigel G. Herron, Mehul R. Vashi, Jane W. Sowards | 2008-09-02 |