Issued Patents All Time
Showing 101–125 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7218143 | Integrated circuit having fast interconnect paths between memory elements and carry logic | — | 2007-05-15 |
| 7215138 | Programmable lookup table with dual input and output terminals in shift register mode | Venu M. Kondapalli, Trevor J. Bauer, Manoj Chirania, Philip D. Costello | 2007-05-08 |
| 7205790 | Programmable integrated circuit providing efficient implementations of wide logic functions | — | 2007-04-17 |
| 7202698 | Integrated circuit having a programmable input structure with bounce capability | Trevor J. Bauer | 2007-04-10 |
| 7199610 | Integrated circuit interconnect structure having reduced coupling between interconnect lines | Ramakrishna K. Tanikella, Sanjiv Stokes | 2007-04-03 |
| 7196543 | Integrated circuit having a programmable input structure with optional fanout capability | Trevor J. Bauer | 2007-03-27 |
| 7193433 | Programmable logic block having lookup table with partial output signal driving carry multiplexer | — | 2007-03-20 |
| 7187200 | Columnar architecture | — | 2007-03-06 |
| 7142442 | Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability | Vasisht Mantra Vadi, David P. Schultz, Jennifer Wong | 2006-11-28 |
| 7132851 | Columnar floorplan | — | 2006-11-07 |
| 7129765 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon | 2006-10-31 |
| 7126406 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon | 2006-10-24 |
| 7110281 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Martin L. Voogel | 2006-09-19 |
| 7109734 | Characterizing circuit performance by separating device and interconnect impact on signal delay | Xiao-Jie Yuan, Michael J. Hart, Zicheng Gary Ling | 2006-09-19 |
| 7095253 | Programmable multi-chip module | — | 2006-08-22 |
| 7089527 | Structures and methods for selectively applying a well bias to portions of a programmable device | Michael J. Hart, Stephen M. Trimberger | 2006-08-08 |
| 7075332 | Six-input look-up table and associated memory control circuitry for use in a field programmable gate array | Venu M. Kondapalli, Ramakrishna K. Tanikella | 2006-07-11 |
| 7071756 | Clock multiplexing system | Vasisht Mantra Vadi | 2006-07-04 |
| 7068072 | Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit | Bernard J. New, Robert O. Conn, Edel M. Young | 2006-06-27 |
| 7064574 | PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets | Martin L. Voogel | 2006-06-20 |
| 7061271 | Six-input look-up table for use in a field programmable gate array | Venu M. Kondapalli, Ramakrishna K. Tanikella | 2006-06-13 |
| 7057413 | Large crossbar switch implemented in FPGA | Peter H. Alfke, Trevor J. Bauer, Colm P. Fewer | 2006-06-06 |
| 7053654 | PLD lookup table including transistors of more than one oxide thickness | Venu M. Kondapalli, Martin L. Voogel | 2006-05-30 |
| 6982451 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi +3 more | 2006-01-03 |
| 6975145 | Glitchless dynamic multiplexer with synchronous and asynchronous controls | Vasisht Mantra Vadi | 2005-12-13 |