Issued Patents All Time
Showing 76–100 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7414430 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon | 2008-08-19 |
| 7402443 | Methods of providing families of integrated circuits with similar dies partially disabled using product selection codes | Raymond C. Pang, Trevor J. Bauer, F. Erich Goetting, Bruce E. Talley | 2008-07-22 |
| 7382157 | Interconnect driver circuits for dynamic logic | Ramakrishna K. Tanikella, Manoj Chirania, Venu M. Kondapalli | 2008-06-03 |
| 7376000 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Martin L. Voogel | 2008-05-20 |
| 7375552 | Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure | Trevor J. Bauer, Manoj Chirania, Venu M. Kondapalli | 2008-05-20 |
| 7372299 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Atul V. Ghia, Adebabay M. Bekele, Suresh M. Menon | 2008-05-13 |
| 7353487 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Suresh M. Menon, Atul V. Ghia +1 more | 2008-04-01 |
| 7345507 | Multi-product die configurable as two or more programmable integrated circuits of different logic capacities | Trevor J. Bauer, F. Erich Goetting, P. Hugo Lamarche, Patrick J. McGuire, Kwansuhk Oh +3 more | 2008-03-18 |
| 7317773 | Double data rate flip-flop | Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2008-01-08 |
| 7314174 | Method and system for configuring an integrated circuit | Vasisht Mantra Vadi, David P. Schultz, Jennifer Wong | 2008-01-01 |
| 7312631 | Structures and methods for avoiding hold time violations in a programmable logic device | Trevor J. Bauer, Ramakrishna K. Tanikella | 2007-12-25 |
| 7301796 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets | Martin L. Voogel | 2007-11-27 |
| 7286382 | Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability | Vasisht Mantra Vadi, David P. Schultz, Jennifer Wong | 2007-10-23 |
| 7279929 | Integrated circuit with programmable routing structure including straight and diagonal interconnect lines | — | 2007-10-09 |
| 7276934 | Integrated circuit with programmable routing structure including diagonal interconnect lines | — | 2007-10-02 |
| 7274214 | Efficient tile layout for a programmable logic device | — | 2007-09-25 |
| 7268587 | Programmable logic block with carry chains providing lookahead functions of different lengths | Tien Duc Pham, Manoj Chirania, Venu M. Kondapalli | 2007-09-11 |
| 7265576 | Programmable lookup table with dual input and output terminals in RAM mode | Venu M. Kondapalli, Trevor J. Bauer, Manoj Chirania, Philip D. Costello | 2007-09-04 |
| 7256612 | Programmable logic block providing carry chain with programmable initialization values | Tien Duc Pham, Philip D. Costello | 2007-08-14 |
| 7253658 | Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure | — | 2007-08-07 |
| 7248491 | Circuit for and method of implementing a content addressable memory in a programmable logic device | Alvin Y. Ching, Raymond C. Pang, Thanh Minh Pham | 2007-07-24 |
| 7242633 | Memory device and method of transferring data in memory device | Alvin Y. Ching, Raymond C. Pang, Thanh Minh Pham | 2007-07-10 |
| 7221186 | Efficient tile layout for a programmable logic device | — | 2007-05-22 |
| 7218143 | Integrated circuit having fast interconnect paths between memory elements and carry logic | — | 2007-05-15 |
| 7218140 | Integrated circuit having fast interconnect paths between carry chain multiplexers and lookup tables | — | 2007-05-15 |