Issued Patents All Time
Showing 126–150 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6949951 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Michael J. Hart, Venu M. Kondapalli, Martin L. Voogel | 2005-09-27 |
| 6933747 | Structures and methods of testing interconnect structures in programmable logic devices | Trevor J. Bauer, Ramakrishna K. Tanikella | 2005-08-23 |
| 6864715 | Windowing circuit for aligning data and clock signals | Trevor J. Bauer, Christopher D. Ebeling, Jason R. Bergendahl, Arthur J. Behiel | 2005-03-08 |
| 6847228 | Carry logic design having simplified timing modeling for a field programmable gate array | Patrick J. Crotty, Tao Pi | 2005-01-25 |
| 6798239 | Programmable gate array having interconnecting logic to support embedded fixed logic circuitry | Stephen M. Douglass, Nigel G. Herron, Mehul R. Vashi, Jane W. Sowards | 2004-09-28 |
| 6798241 | Methods for aligning data and clock signals | Trevor J. Bauer, Christopher D. Ebeling, Jason R. Bergendahl, Arthur J. Behiel | 2004-09-28 |
| 6777978 | Structures and methods for selectively applying a well bias to portions of a programmable device | Michael J. Hart, Stephen M. Trimberger | 2004-08-17 |
| 6777980 | Double data rate flip-flop | Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2004-08-17 |
| 6775342 | Digital phase shifter | John D. Logue, Andrew K. Percey, F. Erich Goetting, Alvin Y. Ching | 2004-08-10 |
| 6768335 | Integrated circuit multiplexer including transistors of more than one oxide thickness | Michael J. Hart, Venu M. Kondapalli, Martin L. Voogel | 2004-07-27 |
| 6768338 | PLD lookup table including transistors of more than one oxide thickness | Venu M. Kondapalli, Martin L. Voogel | 2004-07-27 |
| 6759869 | Large crossbar switch implemented in FPGA | Peter H. Alfke, Trevor J. Bauer, Colm P. Fewer | 2004-07-06 |
| 6708191 | Configurable logic block with and gate for efficient multiplication in FPGAS | Kenneth D. Chapman | 2004-03-16 |
| 6621296 | FPGA lookup table with high speed read decorder | Richard A. Carberry, Trevor J. Bauer | 2003-09-16 |
| 6621325 | Structures and methods for selectively applying a well bias to portions of a programmable device | Michael J. Hart, Daniel Gitlin, Hua Shen, Stephen M. Trimberger | 2003-09-16 |
| 6612546 | Gate valve with delayed retraction of counter plate | Vaclav Myslivec | 2003-09-02 |
| 6603332 | Configurable logic block for PLD with logic gate for combining output with another configurable logic block | Alireza S. Kaviani, Sundararajarao Mohan, Ralph D. Wittig, Bernard J. New | 2003-08-05 |
| 6573749 | Method and apparatus for incorporating a multiplier into an FPGA | Bernard J. New | 2003-06-03 |
| 6529040 | FPGA lookup table with speed read decoder | Richard A. Carberry, Trevor J. Bauer | 2003-03-04 |
| 6525565 | Double data rate flip-flop | Suresh M. Menon, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2003-02-25 |
| 6526557 | Architecture and method for partially reconfiguring an FPGA | Trevor J. Bauer | 2003-02-25 |
| 6522167 | User configurable on-chip memory system | Ahmad R. Ansari, Stephen M. Douglass, Mehul R. Vashi | 2003-02-18 |
| 6493862 | Method for compressing an FPGA bitsream | Jeffrey V. Lindholm | 2002-12-10 |
| 6472909 | Clock routing circuit with fast glitchless switching | — | 2002-10-29 |
| 6448809 | FPGA with a plurality of input reference voltage levels | F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli | 2002-09-10 |