Issued Patents All Time
Showing 176–200 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6204691 | FPGA with a plurality of input reference voltage levels grouped into sets | F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli | 2001-03-20 |
| 6204689 | Input/output interconnect circuit for FPGAs | Andrew K. Percey, Trevor J. Bauer | 2001-03-20 |
| 6201406 | FPGA configurable by two types of bitstreams | Roman Iwanczuk | 2001-03-13 |
| 6201410 | Wide logic gate implemented in an FPGA configurable logic element | Bernard J. New, Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, Roman Iwanczuk | 2001-03-13 |
| 6188091 | FPGA one turn routing structure using minimum diffusion area | — | 2001-02-13 |
| 6163167 | Method for generating an FPGA two turn routing structure with lane changing and minimum diffusion area | — | 2000-12-19 |
| 6154048 | Structure and method for loading narrow frames of data from a wide input bus | Roman Iwanczuk | 2000-11-28 |
| 6144220 | FPGA Architecture using multiplexers that incorporate a logic gate | — | 2000-11-07 |
| 6137307 | Structure and method for loading wide frames of data from a narrow input bus | Roman Iwanczuk | 2000-10-24 |
| 6124731 | Configurable logic element with ability to evaluate wide logic functions | Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, Roman Iwanczuk | 2000-09-26 |
| 6118298 | Structure for optionally cascading shift registers | Trevor J. Bauer, Bruce A. Newgard, William E. Allaire | 2000-09-12 |
| 6107826 | Interconnect structure for FPGA with configurable delay locked loop | Trevor J. Bauer | 2000-08-22 |
| 6107827 | FPGA CLE with two independent carry chains | Bernard J. New, Nicolas John Camilleri, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary +1 more | 2000-08-22 |
| 6097210 | Multiplexer array with shifted input traces | Roman Iwanczuk, David P. Schultz | 2000-08-01 |
| 6072348 | Programmable power reduction in a clock-distribution circuit | Bernard J. New, Trevor J. Bauer | 2000-06-06 |
| 6069489 | FPGA having fast configuration memory data readback | Roman Iwanczuk, David P. Schultz | 2000-05-30 |
| 6051992 | Configurable logic element with ability to evaluate five and six input functions | Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, Roman Iwanczuk | 2000-04-18 |
| 6049227 | FPGA with a plurality of I/O voltage levels | F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli | 2000-04-11 |
| 6020776 | Efficient multiplexer structure for use in FPGA logic blocks | — | 2000-02-01 |
| 5963050 | Configurable logic element with fast feedback paths | Bernard J. New, Nicolas John Camilleri, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary +1 more | 1999-10-05 |
| 5962881 | FPGA layout for a pair of six input multiplexers | — | 1999-10-05 |
| 5942913 | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines | Trevor J. Bauer, Kamal Chaudhary, Sridhar Krishnamurthy | 1999-08-24 |
| 5939930 | Interconnect structure for FPGA using a multiplexer | — | 1999-08-17 |
| 5936424 | High speed bus with tree structure for selecting bus driver | Kamal Chaudhary, Shekhar Bapat, Sridhar Krishnamurthy, Philip D. Costello | 1999-08-10 |
| 5933023 | FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines | — | 1999-08-03 |