Issued Patents All Time
Showing 151–175 of 215 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6448808 | Interconnect structure for a programmable logic device | Kamal Chaudhary, Trevor J. Bauer | 2002-09-10 |
| 6445209 | FPGA lookup table with NOR gate write decoder and high speed read decoder | Trevor J. Bauer, Richard A. Carberry | 2002-09-03 |
| 6429698 | Clock multiplexer circuit with glitchless switching | — | 2002-08-06 |
| 6427156 | Configurable logic block with AND gate for efficient multiplication in FPGAS | Kenneth D. Chapman | 2002-07-30 |
| 6396303 | Expandable interconnect structure for FPGAS | — | 2002-05-28 |
| 6373279 | FPGA lookup table with dual ended writes for ram and shift register modes | Trevor J. Bauer, Richard A. Carberry | 2002-04-16 |
| 6373779 | Block RAM having multiple configurable write modes for use in a field programmable gate array | Raymond C. Pang | 2002-04-16 |
| 6362648 | Multiplexer for implementing logic functions in a programmable logic device | Bernard J. New, Shekhar Bapat, Kamal Chaudhary, Trevor J. Bauer, Roman Iwanczuk | 2002-03-26 |
| 6362650 | Method and apparatus for incorporating a multiplier into an FPGA | Bernard J. New | 2002-03-26 |
| 6353341 | Method and apparatus for discriminating against signal interference | Austin H. Lesea, Peter H. Alfke, Jennifer Wong | 2002-03-05 |
| 6346825 | Block RAM with configurable data width and parity for use in a field programmable gate array | Raymond C. Pang, Trevor J. Bauer | 2002-02-12 |
| 6323681 | Circuits and methods for operating a multiplexer array | Roman Iwanczuk, David P. Schultz | 2001-11-27 |
| 6323682 | FPGA architecture with wide function multiplexers | Trevor J. Bauer | 2001-11-27 |
| 6297665 | FPGA architecture with dual-port deep look-up table RAMS | Trevor J. Bauer | 2001-10-02 |
| 6294930 | FPGA with a plurality of input reference voltage levels | F. Erich Goetting, Scott O. Frake, Venu M. Kondapalli | 2001-09-25 |
| 6292022 | Interconnect structure for a programmable logic device | Kamal Chaudhary, Trevor J. Bauer | 2001-09-18 |
| 6288568 | FPGA architecture with deep look-up table RAMs | Trevor J. Bauer | 2001-09-11 |
| 6282127 | Block RAM with reset to user selected value | Raymond C. Pang, Trevor J. Bauer | 2001-08-28 |
| 6278290 | Method and circuit for operating programmable logic devices during power-up and stand-by modes | — | 2001-08-21 |
| 6262597 | FIFO in FPGA having logic elements that include cascadable shift registers | Trevor J. Bauer, Bruce A. Newgard, William E. Allaire | 2001-07-17 |
| 6255848 | Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA | David P. Schultz, Lawrence C. Hung | 2001-07-03 |
| 6218864 | Structure and method for generating a clock enable signal in a PLD | Jane W. Sowards, Wilson K. Yee | 2001-04-17 |
| 6219305 | Method and system for measuring signal propagation delays using ring oscillators | Robert D. Patrie, Robert W. Wells, Christopher H. Kingsley, Daniel Chung, Robert O. Conn | 2001-04-17 |
| 6204690 | FPGA architecture with offset interconnect lines | Kamal Chaudhary, Trevor J. Bauer | 2001-03-20 |
| 6204695 | Clock-gating circuit for reducing power consumption | Peter H. Alfke, Alvin Y. Ching, Scott O. Frake, Jennifer Wong | 2001-03-20 |