Issued Patents All Time
Showing 51–58 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7096393 | Built-in self-test (BIST) of memory interconnect | Olivier Caty, Ismet Bayraktaroglu | 2006-08-22 |
| 7065724 | Method and apparatus for generating and verifying libraries for ATPG tool | Olivier Caty, Ismet Bayraktaroglu | 2006-06-20 |
| 7020820 | Instruction-based built-in self-test (BIST) of external memory | Olivier Caty, Ismet Bayraktaroglu | 2006-03-28 |
| 6813201 | Automatic generation and validation of memory test models | Kamran Zarrineh, Thomas A. Ziaja | 2004-11-02 |
| 6507925 | Spatial and temporal alignment of a scan dump for debug of scan-based designs | Sridhar Narayanan, Paul J. Dickinson, Gregory S. Clausen, Cary Chin | 2003-01-14 |
| 6263461 | Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit | Timothy Ayres, Ajay Khoche | 2001-07-17 |
| 6088823 | Circuit for efficiently testing memory and shadow logic of a semiconductor integrated circuit | Timothy Ayres, Ajay Khoche | 2000-07-11 |
| 6000050 | Method for minimizing ground bounce during DC parametric tests using boundary scan register | Michio Komoda, Timothy Ayres | 1999-12-07 |