Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7496491 | Delay calculation method capable of calculating delay time with small margin of error | — | 2009-02-24 |
| 7479825 | Clock forming method for semiconductor integrated circuit and program product for the method | — | 2009-01-20 |
| 7127385 | Delay time estimation method and recording medium storing estimation program | Shigeru Kuriyama | 2006-10-24 |
| 7039573 | Method of formulating load model for glitch analysis and recording medium with the method recorded thereon | — | 2006-05-02 |
| 6925624 | Circuit modification method | — | 2005-08-02 |
| 6678849 | Semiconductor integrated circuit and test pattern generation method therefor | Junya Shiraishi | 2004-01-13 |
| 6552551 | Method of producing load for delay time calculation and recording medium | Sigeru Kuriyama | 2003-04-22 |
| 6546537 | Wiring data generation method and wiring data generation apparatus allowing inconsistency between block internal line and block external lines | — | 2003-04-08 |
| 6510404 | Gate delay calculation apparatus and method thereof using parameter expressing RC model source resistance value | Shigeru Kuriyama | 2003-01-21 |
| 6292043 | Semiconductor integrated circuit device | Junya Shiraishi | 2001-09-18 |
| 6076178 | Test circuit and method for DC testing LSI capable of preventing simultaneous change of signals | — | 2000-06-13 |
| 6073265 | Pipeline circuit with a test circuit with small circuit scale and an automatic test pattern generating method for testing the same | — | 2000-06-06 |
| 6000050 | Method for minimizing ground bounce during DC parametric tests using boundary scan register | Timothy Ayres, Amitava Majumdar | 1999-12-07 |
| 5729126 | Master slice LSI with integrated fault detection circuitry | Yoshio Inoue | 1998-03-17 |
| 5619440 | Multiplier circuit with rounding-off function | — | 1997-04-08 |
| 5541861 | Logic simulator | Naoko Omori | 1996-07-30 |
| 5515291 | Apparatus for calculating delay time in logic functional blocks | Naoko Omori | 1996-05-07 |
| 5473548 | Apparatus for computing power consumption of MOS transistor logic function block | Naoko Omori | 1995-12-05 |
| 5444647 | Multiplier circuit and division circuit with a round-off function | — | 1995-08-22 |
| 5438524 | Logic synthesizer | — | 1995-08-01 |
| 5379232 | Logic simulator | — | 1995-01-03 |
| 5347178 | CMOS semiconductor logic circuit with multiple input gates | Mitsuhiro Deguchi | 1994-09-13 |