Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386559 | Access tracking in memory | Cagdas Dirik, Robert M. Walker | 2025-08-12 |
| 12230311 | Aliased row hammer detector | Edmund J. Gieske, Cagdas Dirik, Robert M. Walker, Sujeet Ayyapureddi, Niccolò Izzo +4 more | 2025-02-18 |
| 12217824 | Finite time counting period counting of infinite data streams | Edmund J. Gieske, Amitava Majumdar, Cagdas Dirik, Sujeet Ayyapureddi, Yang Lu +4 more | 2025-02-04 |
| 12182413 | Area-optimized row hammer mitigation | Sujeet Ayyapureddi, Yang Lu, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-12-31 |
| 12153832 | Memory searching component | Robert M. Walker, Paul Rosenfeld | 2024-11-26 |
| 12067270 | Memory device security and row hammer mitigation | Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel +3 more | 2024-08-20 |
| 11893279 | Access tracking in memory | Cagdas Dirik, Robert M. Walker | 2024-02-06 |
| 11775458 | Multiple memory type shared memory bus systems and methods | David A. Roberts, Joseph T. Pawlowski | 2023-10-03 |
| 11768770 | Cache memory addressing | Joseph T. Pawlowski, David A. Roberts | 2023-09-26 |
| 11755515 | Translation system for finer grain memory architectures | Brent Keeth, Richard C. Murphy | 2023-09-12 |
| 11494119 | Memory searching component | Robert M. Walker, Paul Rosenfeld | 2022-11-08 |
| 11436144 | Cache memory addressing | Joseph T. Pawlowski, David A. Roberts | 2022-09-06 |
| 11281608 | Translation system for finer grain memory architectures | Brent Keeth, Richard C. Murphy | 2022-03-22 |
| 11281604 | Multiple memory type shared memory bus systems and methods | David A. Roberts, Joseph T. Pawlowski | 2022-03-22 |
| 10838897 | Translation system for finer grain memory architectures | Brent Keeth, Richard C. Murphy | 2020-11-17 |
| 10628354 | Translation system for finer grain memory architectures | Brent Keeth, Richard C. Murphy | 2020-04-21 |