Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10963248 | Handling effective address synonyms in a load-store unit that operates without address translation | Balaram Sinharoy | 2021-03-30 |
| 10929144 | Speculatively releasing store data before store instruction completion in a processor | Kenneth L. Ward, Hung Q. Le, Dung Q. Nguyen | 2021-02-23 |
| 10877763 | Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor | Brian D. Barrick, Kurt A. Feiste, Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward | 2020-12-29 |
| 10776113 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Balaram Sinharoy | 2020-09-15 |
| 10664275 | Speeding up younger store instruction execution after a sync instruction | Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more | 2020-05-26 |
| 10628166 | Allocating and deallocating reorder queue entries for an out-of-order processor | Balaram Sinharoy | 2020-04-21 |
| 10628158 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Balaram Sinharoy | 2020-04-21 |
| 10606591 | Handling effective address synonyms in a load-store unit that operates without address translation | Balaram Sinharoy | 2020-03-31 |
| 10606590 | Effective address based load store unit in out of order processors | Balaram Sinharoy | 2020-03-31 |
| 10606592 | Handling effective address synonyms in a load-store unit that operates without address translation | Balaram Sinharoy | 2020-03-31 |
| 10606593 | Effective address based load store unit in out of order processors | Balaram Sinharoy | 2020-03-31 |
| 10579387 | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor | Christopher Gonzalez, Balaram Sinharoy | 2020-03-03 |
| 10572257 | Handling effective address synonyms in a load-store unit that operates without address translation | Balaram Sinharoy | 2020-02-25 |
| 10572256 | Handling effective address synonyms in a load-store unit that operates without address translation | Balaram Sinharoy | 2020-02-25 |
| 10534616 | Load-hit-load detection in an out-of-order processor | Christopher Gonzalez, Balaram Sinharoy | 2020-01-14 |
| 10481915 | Split store data queue design for an out-of-order processor | Balaram Sinharoy | 2019-11-19 |
| 10417002 | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-09-17 |
| 10394558 | Executing load-store operations without address translation hardware per load-store unit port | Christopher Gonzalez, Balaram Sinharoy | 2019-08-27 |
| 10324856 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-06-18 |
| 10310988 | Address translation for sending real address to memory subsystem in effective address based load-store unit | Balaram Sinharoy, Shih-Hsiung S. Tung | 2019-06-04 |
| 10067765 | Speeding up younger store instruction execution after a sync instruction | Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt +1 more | 2018-09-04 |
| 9389867 | Speculative finish of instruction execution in a processor core | Sundeep Chadha, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt | 2016-07-12 |
| 9384002 | Speculative finish of instruction execution in a processor core | Sundeep Chadha, Dung Q. Nguyen, David Scott Ray, Benjamin W. Stolt | 2016-07-05 |
| 9086986 | Detection of conflicts between transactions and page shootdowns | Harold W. Cain, III, Hung Q. Le, Shih-Hsiung S. Tung | 2015-07-21 |
| 9086987 | Detection of conflicts between transactions and page shootdowns | Harold W. Cain, III, Hung Q. Le, Shih-Hsiung S. Tung | 2015-07-21 |