Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9971687 | Operation of a multi-slice processor with history buffers storing transaction memory state information | Susan E. Eisen, Kurt A. Feiste, Dung Q. Nguyen, Kenneth L. Ward, Jing Zhang | 2018-05-15 |
| 9952861 | Operation of a multi-slice processor with selective producer instruction types | Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar +2 more | 2018-04-24 |
| 9952874 | Operation of a multi-slice processor with selective producer instruction types | Sundeep Chadha, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar +2 more | 2018-04-24 |
| 9928128 | In-pipe error scrubbing within a processor core | James Wilson Bishop, Marcy E. Byers, Sundeep Chadha, Niels Fricke, Dung Q. Nguyen +1 more | 2018-03-27 |
| 9880847 | Register file mapping | Gregory W. Alexander, Lee Evan Eisen, David A. Schroter | 2018-01-30 |
| 9846614 | ECC scrubbing in a multi-slice microprocessor | James Wilson Bishop, Maarten J. Boersma, Marcy E. Byers, Sundeep Chadha, Jentje Leenstra +2 more | 2017-12-19 |
| 9703614 | Managing a free list of resources to decrease control complexity and reduce power consumption | Gregory W. Alexander | 2017-07-11 |
| 9645637 | Managing a free list of resources to decrease control complexity and reduce power consumption | Gregory W. Alexander | 2017-05-09 |
| 9542233 | Managing a free list of resources to decrease control complexity and reduce power consumption | Gregory W. Alexander | 2017-01-10 |
| 9342307 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Gregory W. Alexander, John W. Ward, III | 2016-05-17 |
| 9075600 | Program status word dependency handling in an out of order microprocessor design | Gregory W. Alexander, Michael Billeci, Fadi Y. Busaba, Bruce C. Giamei, David A. Schroter | 2015-07-07 |
| 9069546 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Gregory W. Alexander, John W. Ward, III | 2015-06-30 |
| 8984261 | Store data forwarding with no memory model restrictions | Barry W. Krumm, James R. Mitchell, Bradley Nelson, Aaron Tsai, Chung-Lung K. Shum +1 more | 2015-03-17 |
| 8683180 | Intermediate register mapper | Michael Billeci, Lee Evan Eisen | 2014-03-25 |
| 8661230 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions | Gregory W. Alexander, John W. Ward, III | 2014-02-25 |
| 8645670 | Specialized store queue and buffer design for silent store implementation | Chung-Lung K. Shum, Aaron Tsai | 2014-02-04 |
| 8627047 | Store data forwarding with no memory model restrictions | Aaron Tsai, Barry W. Krumm, James R. Mitchell, Bradley Nelson, Chung-Lung K. Shum +1 more | 2014-01-07 |
| 8468306 | Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions | Aaron Tsai, Barry W. Krumm, James R. Mitchell, Bradley Nelson, Chung-Lung K. Shum +1 more | 2013-06-18 |
| 8250336 | Method, system and computer program product for storing external device result data | Chung-Lung K. Shum, Thomas Koehler, Aaron Tsai | 2012-08-21 |
| 7953932 | System and method for avoiding deadlocks when performing storage updates in a multi-processor environment | Chung-Lung K. Shum, Aaron Tsai, Charles F. Webb | 2011-05-31 |
| 7904697 | Load register instruction short circuiting method | Brian W. Curran, Lee Evan Eisen | 2011-03-08 |
| 7870314 | Method and system for implementing store buffer allocation | Vimal M. Kapadia, Chung-Lung K. Shum, Aaron Tsai | 2011-01-11 |
| 7769984 | Dual-issuance of microprocessor instructions using dual dependency matrices | Gregory W. Alexander, Lee Evan Eisen, John W. Ward, III | 2010-08-03 |
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system | Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray, David Shippy, Takeki Osanai | 2010-08-03 |
| 7730290 | Systems for executing load instructions that achieve sequential load consistency | Kimberly M. Fernsler, Dwain A. Hicks, Takeki Osanai, David Scott Ray | 2010-06-01 |