VB

Valeria Bertacco

University of Michigan: 10 patents #137 of 4,352Top 4%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
📍 Ann Arbor, MI: #689 of 6,071 inventorsTop 15%
🗺 Michigan: #6,947 of 86,293 inventorsTop 9%
Overall (All Time): #366,765 of 4,157,543Top 9%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
12105855 Privacy-enhanced computation via sequestered encryption Todd Michael Austin, Alexander Kisil 2024-10-01
11868283 Hybrid on/off-chip memory architecture for graph analytics Abraham Addisie 2024-01-09
11748490 Computer system with moving target defenses against vulnerability attacks Todd Michael Austin, Mark Gallagher, Baris Kasikci 2023-09-05
11748521 Privacy-enhanced computation via sequestered encryption Todd Michael Austin, Alexander Kisil 2023-09-05
11232212 Computer system with moving target defenses against vulnerability attacks Todd Michael Austin, Mark Gallagher, Baris Kasikci 2022-01-25
9645882 Field repairable logic Todd Michael Austin, Ilya Wagner 2017-05-09
9411007 System and method for statistical post-silicon validation Andrew DeOrio, Daya Shanker Khudia 2016-08-09
8738349 Gate-level logic simulator using multiple processor architectures Debapriya Chatterjee, Andrew DeOrio 2014-05-27
8365110 Automatic error diagnosis and correction for RTL designs Kai-Hui Chang, Ilya Wagner, Igor Markov 2013-01-29
8341473 Microprocessor and method for detecting faults therein Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke 2012-12-25
8051368 Microprocessor and method for detecting faults therein Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke 2011-11-01
7966538 Microprocessor and method for detecting faults therein Todd Michael Austin, Smitha Shyam, Kypros Constantinides, Sujay Phadke 2011-06-21
6493841 Method and apparatus for determining expected values during circuit design verification Won-Sub Kim, Daniel Marcos Chapiro, Sandro H. Pintz 2002-12-10