Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9367263 | Transaction check instruction for memory transactions | Guy L. Guthrie, Cathy May, Derek E. Williams | 2016-06-14 |
| 9348763 | Asymmetric co-existent address translation structure formats | Anthony J. Bybell, David D. Dukro, Michael K. Gschwind | 2016-05-24 |
| 9342454 | Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses | Guy L. Guthrie, Cathy May, Derek E. Williams | 2016-05-17 |
| 9330023 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-05-03 |
| 9323692 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-26 |
| 9317443 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-19 |
| 9311249 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-12 |
| 9280488 | Asymmetric co-existent address translation structure formats | Anthony J. Bybell, David D. Dukro, Michael K. Gschwind | 2016-03-08 |
| 9268598 | Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories | Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Charles B. Hall, Hung Q. Le +1 more | 2016-02-23 |
| 9251088 | Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation | Michael K. Gschwind, Benjamin Herrenschmidt | 2016-02-02 |
| 9244846 | Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses | Cathy May, Derek E. Williams | 2016-01-26 |
| 9081607 | Conditional transaction abort and precise abort handling | Robert J. Blainey, Harold W. Cain, III, Hung Q. Le, Cathy May | 2015-07-14 |
| 9047079 | Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition | Becky Bruce, Giles R. Frazier, Kumar K. Gala, Cathy May, Michael D. Snyder +2 more | 2015-06-02 |
| 8856453 | Persistent prefetch data stream settings | Jason N. Dale, Miles Robert Dooley, Richard J. Eickemeyer, Yaoqing Gao, Francis Patrick O'Connell +1 more | 2014-10-07 |
| 8645667 | Operating system management of address-translation-related data structures and hardware lookasides | Michal Ostrowski, Andrew Henry Wottreng | 2014-02-04 |
| 8615644 | Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition | Becky Bruce, Giles R. Frazier, Kumar K. Gala, Cathy May, Michael D. Snyder +2 more | 2013-12-24 |
| 8589657 | Operating system management of address-translation-related data structures and hardware lookasides | Michal Ostrowski, Andrew Henry Wottreng | 2013-11-19 |
| 8544022 | Transactional memory preemption mechanism | Richard Louis Arndt, Harold W. Cain, III, Cathy May | 2013-09-24 |
| 8424015 | Transactional memory preemption mechanism | Richard Louis Arndt, Harold W. Cain, III, Cathy May | 2013-04-16 |
| 8176254 | Specifying an access hint for prefetching limited use data in a cache hierarchy | Guy L. Guthrie, Cathy May, Balaram Sinharoy, Peter K. Szwed | 2012-05-08 |
| 8140759 | Specifying an access hint for prefetching partial cache block data in a cache hierarchy | Guy L. Guthrie, Cathy May, Ramakrishnan Rajamony, Balaram Sinharoy, William J. Starke +1 more | 2012-03-20 |
| 7908457 | Retaining an association between a virtual address based buffer and a user space application that owns the buffer | Richard Louis Arndt, Aaron C. Brown, Gregory F. Pfister, Renato J. Recio, Steven M. Thurber | 2011-03-15 |
| 7904661 | Data stream prefetching in a microprocessor | Eric Jason Fluhr, John B. Griswell, Jr., Hung Q. Le, Cathy May, Francis Patrick O'Connell +2 more | 2011-03-08 |
| 7827343 | Method and apparatus for providing accelerator support in a bus protocol | Steven M. Thurber, Andrew Henry Wottreng | 2010-11-02 |
| 7350029 | Data stream prefetching in a microprocessor | Eric Jason Fluhr, John B. Griswell, Jr., Hung Q. Le, Cathy May, Francis Patrick O'Connell +2 more | 2008-03-25 |