Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Configurable I/O address translation data structure

Configurable I/O address translation data structure

US Patent 10241923 · Granted Mar 26, 2019

Estimated economic value: $2,148,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Detecting redundant power feeds2025
Secure memory isolation for secure endpoints2024
Techniques for handling escalation of interrupts in a data processing system2023
Process-based virtualization system for executing a secure application process2022
Translation load instruction with access protection2022
Promotion of ERAT cache entries2022
Managing direct memory access2021
Managing efficient selection of a particular processor thread for handling an in2021
Peripheral component interconnect express (PCIE) network with input/output (I/O)2021
Live partition mobility enabled hardware accelerator address translation fault r2020
Interruptible translation entry invalidation in a multithreaded data processing 2020
Snoop invalidate filter for distributed memory management unit to reduce snoop i2020