Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7624256 | System and method wherein conditional instructions unconditionally provide output | Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Kenneth Alan Dockser, Michael Scott McIlvaine | 2009-11-24 |
| 7617387 | Methods and system for resolving simultaneous predicted branch instructions | Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2009-11-10 |
| 7587580 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Michael Scott McIlvaine | 2009-09-08 |
| 7568070 | Instruction cache having fixed number of variable length instructions | Jeffrey Todd Bridges, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2009-07-28 |
| 7478228 | Apparatus for generating return address predictions for implicit and explicit subroutine calls | Brian Michael Stempel, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2009-01-13 |
| 7424563 | Two-level interrupt service routine | Michael Egnoah Birenbach, Gregory Brookshire, James Norris Dieffenderfer, Stephen G. Geist, Richard A. Moore +1 more | 2008-09-09 |
| 7421568 | Power saving methods and apparatus to selectively enable cache bits based on known processor state | Brian Michael Stempel, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-09-02 |
| 7415638 | Pre-decode error handling via branch correction | Brian Michael Stempel, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-08-19 |
| 7406613 | Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions | James Norris Dieffenderfer, Thomas Andrew Sartorius, Brian Michael Stempel | 2008-07-29 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary | Brian Michael Stempel, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-07-22 |
| 7376815 | Methods and apparatus to insure correct predecode | James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-05-20 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2008-04-29 |
| 7278012 | Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions | Thomas Andrew Sartorius, Brian Michael Stempel, Jeffrey Todd Bridges, James Norris Dieffenderfer | 2007-10-02 |
| 7210024 | Conditional instruction execution via emissary instruction for condition evaluation | Michael Scott McIlvaine, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2007-04-24 |
| 7203826 | Method and apparatus for managing a return stack | James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2007-04-10 |
| 7093100 | Translation look aside buffer (TLB) with increased translational capacity for multi-threaded computer processes | Jeffrey Todd Bridges, Les M. DeBruyne, Robert L. Goldiez, Michael Scott McIlvaine, Thomas Andrew Sartorius | 2006-08-15 |
| 6948053 | Efficiently calculating a branch target address | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Thomas Philip Speier | 2005-09-20 |
| 6816962 | Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Thomas Philip Speier | 2004-11-09 |
| 6513134 | System and method for tracing program execution within a superscalar processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2003-01-28 |
| D271054 | Window vent | — | 1983-10-18 |