Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8452831 | Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operations | Jeffrey S. Brooks | 2013-05-28 |
| 8438208 | Processor and method for implementing instruction support for multiplication of large operands | Jeffrey S. Brooks, Robert T. Golla, Paul J. Jordan | 2013-05-07 |
| 8417961 | Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC) | Gregory F. Grohoski, Lawrence Spracklen | 2013-04-09 |
| 8358780 | Execution unit for performing the data encryption standard | Leonard Rarick | 2013-01-22 |
| 8356185 | Apparatus and method for local operand bypassing for cryptographic instructions | Gregory F. Grohoski, Robert T. Golla | 2013-01-15 |
| 8239440 | Processor which implements fused and unfused multiply-add instructions in a pipelined manner | Jeffrey S. Brooks | 2012-08-07 |
| 8195919 | Handling multi-cycle integer operations for a multi-threaded processor | Robert T. Golla, Manish K. Shah, Jeffrey S. Brooks | 2012-06-05 |
| 8195923 | Methods and mechanisms to support multiple features for a number of opcodes | Lawrence Spracklen, Gregory F. Grohoski, Robert T. Golla | 2012-06-05 |
| 8078942 | Register error correction of speculative data in an out-of-order processor | Paul J. Jordan | 2011-12-13 |
| 8073141 | Execution unit for performing the data encryption standard | Leonard Rarick | 2011-12-06 |
| 7941642 | Method for selecting between divide instructions associated with respective threads in a multi-threaded processor | Robert T. Golla, Jeffrey S. Brooks | 2011-05-10 |
| 7795899 | Enabling on-chip features via efuses | Gregory F. Grohoski, Thomas A. Ziaja, Lawrence Spracklen | 2010-09-14 |
| 7720219 | Apparatus and method for implementing a hash algorithm word buffer | Leonard Rarick, Gregory F. Grohoski | 2010-05-18 |
| 7711955 | Apparatus and method for cryptographic key expansion | Leonard Rarick, Gregory F. Grohoski | 2010-05-04 |
| 7684563 | Apparatus and method for implementing a unified hash algorithm pipeline | Leonard Rarick, Gregory F. Grohoski | 2010-03-23 |
| 7620821 | Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software | Gregory F. Grohoski, Leonard Rarick | 2009-11-17 |
| 7571284 | Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor | Manish K. Shah | 2009-08-04 |
| 7570760 | Apparatus and method for implementing a block cipher algorithm | Gregory F. Grohoski | 2009-08-04 |
| 7539720 | Low latency integer divider and integration with floating point divider and method | Jeffrey S. Brooks, Paul J. Jagodik | 2009-05-26 |
| 7523330 | Thread-based clock enabling in a multi-threaded processor | Robert T. Golla, Jeffrey S. Brooks | 2009-04-21 |
| 7478225 | Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor | Jeffrey S. Brooks, Robert T. Golla | 2009-01-13 |
| 7443981 | Execution unit for performing the data encryption standard | Leonard Rarick | 2008-10-28 |
| 7437538 | Apparatus and method for reducing execution latency of floating point operations having special case operands | Jeffrey S. Brooks | 2008-10-14 |
| 7433912 | Multiplier structure supporting different precision multiplication operations | Paul J. Jagodik, Jeffrey S. Brooks | 2008-10-07 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units | Jike Chong, Gregory F. Grohoski | 2008-04-01 |