| 9047116 |
Context switch data prefetching in multithreaded computer |
Jeffrey Powers Bradford, Harold F. Kossman |
2015-06-02 |
| 8539201 |
Transposing array data on SIMD multi-core processor architectures |
Jeffrey S. McAllister, Nelson Ramirez, Mark A. Bransford |
2013-09-17 |
| 8484276 |
Processing array data on SIMD multi-core processor architectures |
David Glenn Carlson, Travis M. Drucker, Jeffrey S. McAllister, Nelson Ramirez |
2013-07-09 |
| 8396267 |
Correcting subject motion in multiple resolutions in magnetic resonance imaging |
David S. Lake, Armando Manduca, Jeffrey S. McAllister, Nelson Ramirez |
2013-03-12 |
| 8140833 |
Implementing polymorphic branch history table reconfiguration |
Jeffrey Powers Bradford, Richard J. Eickemeyer, Timothy H. Heil, Harold F. Kossman |
2012-03-20 |
| 8141098 |
Context switch data prefetching in multithreaded computer |
Jeffrey Powers Bradford, Harold F. Kossman |
2012-03-20 |
| 8060783 |
Distributed runtime diagnostics in hierarchical parallel environments |
Jeffrey S. McAllister, Nelson Ramirez |
2011-11-15 |
| 7647590 |
Parallel computing system using coordinator and master nodes for load balancing and distributing work |
Charles J. Archer, Joseph D. Ratterman, Albert Sidelnik, Brian E. Smith |
2010-01-12 |
| 7617499 |
Context switch instruction prefetching in multithreaded computer |
Jeffrey Powers Bradford, Harold F. Kossman |
2009-11-10 |
| 7493621 |
Context switch data prefetching in multithreaded computer |
Jeffrey Powers Bradford, Harold F. Kossman |
2009-02-17 |
| 7096470 |
Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure |
Jeffrey Douglas Brown, Harold F. Kossman |
2006-08-22 |
| 6965986 |
Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate |
Harold F. Kossman |
2005-11-15 |
| 6324620 |
Dynamic DASD data management and partitioning based on access frequency utilization and capacity |
Patrick James Christenson, Michael J. Corrigan, Thomas R. Crowley, Michael S. Faunce, Michael James McDermott +3 more |
2001-11-27 |
| 6049867 |
Method and system for multi-thread switching only when a cache miss occurs at a second or higher level |
Richard J. Eickemeyer, Ross E. Johnson, Harold F. Kossman, Steven R. Kunkel, James Allen Rose |
2000-04-11 |
| 4857765 |
Noise control in an integrated circuit chip |
Joseph J. Cahill, Charles L. Johnson, Steven D. Lewis, Bruce R. Petz |
1989-08-15 |
