Issued Patents All Time
Showing 51–71 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7788452 | Method and apparatus for tracking cached addresses for maintaining cache coherency in a computer system having multiple caches | Duane A. Averill, David A. Shedivy, Martha E. Voytovich | 2010-08-31 |
| 7752413 | Method and apparatus for communicating between threads | Jon K. Kriegel, Eric O. Mejdrich, Robert A. Shearer | 2010-07-06 |
| 7725660 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Bernard C. Drerup, Charles Ray Johns, David J. Krolak +2 more | 2010-05-25 |
| 7669013 | Directory for multi-node coherent bus | Gary Dale Carpenter, Scott Douglas Clark, Bernard C. Drerup, Charles Ray Johns, David J. Krolak +2 more | 2010-02-23 |
| 7577794 | Low latency coherency protocol for a multi-chip multiprocessor system | Bruce Beukema, Jon K. Kriegel, Eric O. Mejdrich, Sandra S. Woodward | 2009-08-18 |
| 7475190 | Direct access of cache lock set data without backing memory | Eric O. Mejdrich, Sandra S. Woodward | 2009-01-06 |
| 7461268 | E-fuses for storing security version data | Robert Allen Drehmel, William E. Hall | 2008-12-02 |
| 7355601 | System and method for transfer of data between processors using a locked set, head and tail pointers | Jeffrey Andrews, Nicholas R. Baker, J. Andrew Goossen, Eric O. Mejdrich, Sandra S. Woodward | 2008-04-08 |
| 7305524 | Snoop filter directory mechanism in coherency shared memory system | Eric O. Mejdrich, Jon K. Kriegel, Sandra S. Woodward | 2007-12-04 |
| 7013375 | Configurable directory allocation | John Michael Borkenhagen, Philip Hillier | 2006-03-14 |
| 6557069 | Processor-memory bus architecture for supporting multiple processors | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella, George Wayne Nation | 2003-04-29 |
| 6526469 | Bus architecture employing varying width uni-directional command bus | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2003-02-25 |
| 6260090 | Circuit arrangement and method incorporating data buffer with priority-based data storage | Ronald Edward Fuhs, Kenneth Claude Hinz, David A. Shedivy | 2001-07-10 |
| 6247100 | Method and system for transmitting address commands in a multiprocessor system | Robert Allen Drehmel, Kent Harold Haselhorst, James Anthony Marcella | 2001-06-12 |
| 6088768 | Method and system for maintaining cache coherence in a multiprocessor-multicache environment having unordered communication | Donald Francis Baldus, Nancy Joan Duffield, John C. Willis, Frederick J. Ziegler | 2000-07-11 |
| 6006255 | Networked computer system and method of communicating using multiple request packet classes to prevent deadlock | George Wayne Nation, Kenneth M. Valk | 1999-12-21 |
| 5805837 | Method for optimizing reissue commands in master-slave processing systems | George Wayne Nation | 1998-09-08 |
| 5761721 | Method and system for cache coherence despite unordered interconnect transport | Donald Francis Baldus, Nancy Joan Duffield, John C. Willis, Frederick J. Ziegler | 1998-06-02 |
| 5749087 | Method and apparatus for maintaining n-way associative directories utilizing a content addressable memory | George Wayne Nation, Kenneth M. Valk | 1998-05-05 |
| 5604882 | System and method for empty notification from peer cache units to global storage control unit in a multiprocessor data processing system | John C. Willis, Donald Francis Baldus, Frederick J. Ziegler, Lishing Liu | 1997-02-18 |
| 5168571 | System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data | John D. Irish, David W. Sollender | 1992-12-01 |