Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10380048 | Suspend and resume in a time shared coprocessor | Bulent Abali, Craig B. Agricola, Bartholomew Blaner, John J. Reilly, Dorothy Marie Thelen | 2019-08-13 |
| 9921986 | Suspend and resume in a time shared coprocessor | Bulent Abali, Craig B. Agricola, Bartholomew Blaner, John J. Reilly, Dorothy Marie Thelen | 2018-03-20 |
| 9852095 | Suspend and resume in a time shared coprocessor | Bulent Abali, Craig B. Agricola, Bartholomew Blaner, John J. Reilly, Dorothy Marie Thelen | 2017-12-26 |
| 9740629 | Tracking memory accesses when invalidating effective address to real address translations | Bartholomew Blaner, Jay G. Heaslip, Jeffrey A. Stuecheli | 2017-08-22 |
| 9727483 | Tracking memory accesses when invalidating effective address to real address translations | Bartholomew Blaner, Jay G. Heaslip, Jeffrey A. Stuecheli | 2017-08-08 |
| 9286129 | Termination of requests in a distributed coprocessor system | Brian Mitchell Bass, Bartholomew Blaner, Jay G. Heaslip, Robert D. Herzl, Ross Boyd Leavens | 2016-03-15 |
| 9251108 | Managing access to shared buffer resources | Brian Mitchell Bass | 2016-02-02 |
| 9229868 | Data recovery for coherent attached processor proxy | Bartholomew Blaner, Joseph Gerald McDonald, Michael S. Siegel, Jeff A. Stuecheli | 2016-01-05 |
| 8938587 | Data recovery for coherent attached processor proxy | Bartholomew Blaner, Joseph Gerald McDonald, Michael S. Siegel, Jeff A. Stuecheli | 2015-01-20 |
| 8667223 | Shadow registers for least recently used data in cache | Thomas Chadwick, Robert D. Herzl, Arnold S. Tran | 2014-03-04 |
| 8341588 | Semiconductor layer forming method and structure | Robert D. Herzl, Robert S. Horton, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-12-25 |
| 8181148 | Method for identifying and implementing flexible logic block logic for easy engineering changes | Robert D. Herzl, Robert S. Horton, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-05-15 |
| 8141028 | Structure for identifying and implementing flexible logic block logic for easy engineering changes | Robert D. Herzl, Robert S. Horton, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-03-20 |
| 8060845 | Minimizing impact of design changes for integrated circuit designs | Robert D. Herzl, Robert S. Horton, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2011-11-15 |
| 7787577 | Asynchronous interface methods and apparatus | Seetharam Gundurao, Clarence R. Ogilvie, Nishant Sharma, Richard N. Wilson | 2010-08-31 |
| 7480888 | Design structure for facilitating engineering changes in integrated circuits | Clarence R. Ogilvie, Charles B. Winn, David W. Milton, Nitin Sharma, Paul M. Schanely +4 more | 2009-01-20 |
| 7319729 | Asynchronous interface methods and apparatus | Seetharam Gundurao, Clarence R. Ogilvie, Nishant Sharma, Richard N. Wilson | 2008-01-15 |
| 6157981 | Real time invariant behavior cache | Bartholomew Blaner, Henry Harvey Burkhart, Robert D. Herzl, Clarence R. Ogilvie, Arnold S. Tran | 2000-12-05 |
| 5619715 | Hardware implementation of string instructions | Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Thomas W. Seigendall, Robert A. Skaggs +1 more | 1997-04-08 |
| 5608887 | Method of processing data strings | Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Thomas W. Seigendall, Robert A. Skaggs +1 more | 1997-03-04 |
| 5465374 | Processor for processing data string by byte-by-byte | Robert M. Dinkjian, Lisa C. Heller, Steven R. Kordus, Thomas W. Seigendall, Robert A. Skaggs +1 more | 1995-11-07 |
| 5269009 | Processor system with improved memory transfer means | Robert D. Herzl, Linda L. Quinn, David A. Schroter, Allan Rowe Steel, Joseph L. Temple, III | 1993-12-07 |