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Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines |
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Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines |
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Techniques for write-after-write ordering in a coherency managed processor system that employs a command pipeline |
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2008-11-18 |
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2006-11-28 |
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2004-12-07 |
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2003-07-01 |
