Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10169500 | Critical path delay prediction | Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie +2 more | 2019-01-01 |
| 10006964 | Chip performance monitoring system and method | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2018-06-26 |
| 9383766 | Chip performance monitoring system and method | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2016-07-05 |
| 9367493 | Method and system of communicating between peer processors in SoC environment | Robert J. Devins, Pascal A. Nsame | 2016-06-14 |
| 9188643 | Flexible performance screen ring oscillator within a scan chain | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2015-11-17 |
| 9128151 | Performance screen ring oscillator formed from paired scan chains | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2015-09-08 |
| 9097765 | Performance screen ring oscillator formed from multi-dimensional pairings of scan chains | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2015-08-04 |
| 8754696 | Ring oscillator | Margaret R. Charlebois, Rashmi D. Chatty, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie +3 more | 2014-06-17 |
| 8736340 | Differential clock signal generator | — | 2014-05-27 |
| 8464199 | Circuit design using design variable function slope sensitivity | Margaret R. Charlebois, Christopher D. Hanudel, Robert D. Herzl, Clarence R. Ogilvie, Paul M. Schanely +1 more | 2013-06-11 |
| 8416900 | Method and circuit for dynamically changing the frequency of clock signals | Jason Rotella | 2013-04-09 |
| 8341588 | Semiconductor layer forming method and structure | Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-12-25 |
| 8300752 | Method, circuit, and design structure for capturing data across a pseudo-synchronous interface | Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, Clarence R. Ogilvie, Jack R. Smith | 2012-10-30 |
| 8189723 | Method, circuit, and design structure for capturing data across a pseudo-synchronous interface | Malede W. Berhanu, Christopher D. Hanudel, Mark W. Kuemerle, Clarence R. Ogilvie, Jack R. Smith | 2012-05-29 |
| 8181148 | Method for identifying and implementing flexible logic block logic for easy engineering changes | Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-05-15 |
| 8140314 | Optimal bus operation performance in a logic simulation environment | Robert J. Devins | 2012-03-20 |
| 8141028 | Structure for identifying and implementing flexible logic block logic for easy engineering changes | Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2012-03-20 |
| 8060845 | Minimizing impact of design changes for integrated circuit designs | Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, Clarence R. Ogilvie, Paul M. Schanely +3 more | 2011-11-15 |
| 7996807 | Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method | Gary D. Grise, Vikram Iyengar, David E. Lackey | 2011-08-09 |
| 7917348 | Method of switching external models in an automated system-on-chip integrated circuit design verification system | Robert J. Devins, Robert D. Herzl | 2011-03-29 |
| 7863949 | Circuit and design structure for synchronizing multiple digital signals | — | 2011-01-04 |
| 7849362 | Method and system of coherent design verification of inter-cluster interactions | Robert J. Devins, Pascal A. Nsame | 2010-12-07 |
| 7768325 | Circuit and design structure for synchronizing multiple digital signals | — | 2010-08-03 |
| 7729877 | Method and system for logic verification using mirror interface | Robert J. Devins, Paul Ferro, Peter Dean LaFauci, Kenneth A. Mahler | 2010-06-01 |
| 7711534 | Method and system of design verification | Robert J. Devins, Pascal A. Nsame | 2010-05-04 |