Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8793433 | Digital data processing apparatus having multi-level register file | Nathan Samuel Nunamaker, Kenichi Tsuchiya | 2014-07-29 |
| 7917700 | Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state | John D. Irish, Chad B. McBride | 2011-03-29 |
| 7284092 | Digital data processing apparatus having multi-level register file | Nathan Samuel Nunamaker, Kenichi Tsuchiya | 2007-10-16 |
| 7187863 | Identifying substreams in parallel/serial data link | Susan M. Cox, Mark J. Hickey, Dale J. Thomforde, Frederick J. Ziegler | 2007-03-06 |
| 7079528 | Data communication method | Frederick J. Ziegler, Mark J. Hickey, Susan M. Cox, Dale J. Thomforde, Robert Neill Newshutz | 2006-07-18 |
| 7065101 | Modification of bus protocol packet for serial data synchronization | Frederick J. Ziegler, Mark J. Hickey, Susan M. Cox, Dale J. Thomforde | 2006-06-20 |
| 6052708 | Performance monitoring of thread switch events in a multithreaded processor | William T. Flynn, Troy D. Larsen | 2000-04-18 |
| 5970439 | Performance monitoring in a data processing system | Frank Eliot Levine, Charles P. Roth, Edward Hugh Welbon | 1999-10-19 |
| 5862371 | Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring | Frank Eliot Levine, William J. Starke, Edward Hugh Welbon | 1999-01-19 |
| 5835705 | Method and system for performance per-thread monitoring in a multithreaded processor | Troy D. Larsen, Andrew Henry Wottreng | 1998-11-10 |