Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6871267 | Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency | Gary Lippert | 2005-03-22 |
| 6823431 | Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency | Gary Lippert | 2004-11-23 |
| 6557084 | Apparatus and method to improve performance of reads from and writes to shared memory locations | Sheldon B. Levenstein, Gary Lippert | 2003-04-29 |
| 6425060 | Circuit arrangement and method with state-based transaction scheduling | Farnaz Mounes-Toussi | 2002-07-23 |
| 6351791 | Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses | Gary Lippert, Farnaz Mounes-Toussi | 2002-02-26 |
| 6314491 | Peer-to-peer cache moves in a multiprocessor data processing system | Gary Lippert, John D. Irish | 2001-11-06 |
| 6269425 | Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system | Farnaz Mounes-Toussi | 2001-07-31 |
| 6260117 | Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency | Gary Lippert | 2001-07-10 |
| 6035424 | Method and apparatus for tracking processing of a command | Peder James Paulson | 2000-03-07 |
| 6000012 | Method and apparatus for prioritizing and routing commands from a command source to a command sink | Peder James Paulson | 1999-12-07 |
| 6000011 | Multi-entry fully associative transition cache | Farnaz Mounes-Toussi, Peder James Paulson, John D. Irish, Lyle Edwin Grosbach | 1999-12-07 |
| 4996660 | Selection of divisor multipliers in a floating point divide circuit | Thomas J. Beacom | 1991-02-26 |
| 4979142 | Two-bit floating point divide circuit with single carry-save adder | Richard G. Allen | 1990-12-18 |
| 4975868 | Floating-point processor having pre-adjusted exponent bias for multiplication and division | — | 1990-12-04 |
| 4941120 | Floating point normalization and rounding prediction circuit | Jeffrey Douglas Brown, Scott A. Hilker, Daniel Stasiak | 1990-07-10 |
| 4926370 | Method and apparatus for processing postnormalization and rounding in parallel | Jeffrey Douglas Brown, Scott A. Hilker, Daniel Stasiak | 1990-05-15 |