Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651143 | Cache management using a buffer for invalidation requests | — | 2003-11-18 |
| 6615375 | Method and apparatus for tolerating unrecoverable errors in a multi-processor data processing system | Nicholas Poleschuk | 2003-09-02 |
| 6425060 | Circuit arrangement and method with state-based transaction scheduling | Donald Lee Freerksen | 2002-07-23 |
| 6351791 | Circuit arrangement and method of maintaining cache coherence utilizing snoop response collection logic that disregards extraneous retry responses | Donald Lee Freerksen, Gary Lippert | 2002-02-26 |
| 6269425 | Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system | Donald Lee Freerksen | 2001-07-31 |
| 6098152 | Method and apparatus for miss sequence cache block replacement utilizing a most recently used state | — | 2000-08-01 |
| 6000011 | Multi-entry fully associative transition cache | Donald Lee Freerksen, Peder James Paulson, John D. Irish, Lyle Edwin Grosbach | 1999-12-07 |