Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6119202 | Method and apparatus to interleave level 1 data cache line fill data between system bus and level 2 data cache for improved processor performance | John Michael Borkenhagen | 2000-09-12 |
| 6088788 | Background completion of instruction and associated fetch request in a multithread processor | John Michael Borkenhagen, Richard J. Eickemeyer, Sheldon B. Levenstein, Andrew Henry Wottreng, Duane A. Averill | 2000-07-11 |