Issued Patents All Time
Showing 26–50 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9442736 | Techniques for selecting a predicted indirect branch address from global and local caches | Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, Douglas R. G. Logan | 2016-09-13 |
| 9189365 | Hardware-assisted program trace collection with selectable call-signature capture | Giles R. Frazier, Brian R. Mestan, Mauricio J. Serrano | 2015-11-17 |
| 9170920 | Identifying and tagging breakpoint instructions for facilitation of software debug | Brian R. Konigsburg | 2015-10-27 |
| 9081895 | Identifying and tagging breakpoint instructions for facilitation of software debug | Brian R. Konigsburg | 2015-07-14 |
| 9069563 | Reducing store-hit-loads in an out-of-order processor | Brian R. Konigsburg, Brian R. Mestan, David Mui | 2015-06-30 |
| 8943301 | Storing branch information in an address table of a processor | Brian R. Konigsburg, Wolfram Sauer, Samuel Thomas | 2015-01-27 |
| 8943299 | Operating a stack of information in an information handling system | Kattamuri Ekanadham, Brian R. Konigsburg, Jose E. Moreira, David Mui, Il Park | 2015-01-27 |
| 8868886 | Task switch immunized performance monitoring | Giles R. Frazier, Brian R. Mestan | 2014-10-21 |
| 8635408 | Controlling power of a cache based on predicting the instruction cache way for high power applications | Sheldon B. Levenstein | 2014-01-21 |
| 8635621 | Method and apparatus to implement software to hardware thread priority | Jeffrey R. Summers | 2014-01-21 |
| 8370671 | Saving power by powering down an instruction fetch array based on capacity history of instruction buffer | — | 2013-02-05 |
| 8131976 | Tracking effective addresses in an out-of-order processor | Richard W. Doing, Susan E. Eisen, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy +3 more | 2012-03-06 |
| 7984280 | Storing branch information in an address table of a processor | Brian R. Konigsburg, Wolfram Sauer, Samuel Thomas | 2011-07-19 |
| 7962722 | Branch target address cache with hashed indices | Sheldon B. Levenstein, Lixin Zhang | 2011-06-14 |
| 7890738 | Method and logical apparatus for managing processing system resource use for speculative execution | Lee Evan Eisen, Francis Patrick O'Connell, Wolfram Sauer | 2011-02-15 |
| 7877586 | Branch target address cache selectively applying a delayed hit | Lixin Zhang | 2011-01-25 |
| 7865705 | Branch target address cache including address type tag bit | Lixin Zhang | 2011-01-04 |
| 7844807 | Branch target address cache storing direct predictions | Lixin Zhang | 2010-11-30 |
| 7809933 | System and method for optimizing branch logic for handling hard to predict indirect branches | Wolfram Sauer | 2010-10-05 |
| 7783870 | Branch target address cache | William E. Speight, Lixin Zhang | 2010-08-24 |
| 7689816 | Branch prediction with partially folded global history vector for reduced XOR operation time | — | 2010-03-30 |
| 7657783 | Apparatus and computer program product for testing ability to recover from cache directory errors | — | 2010-02-02 |
| 7487334 | Branch encoding before instruction cache write | Brian R. Konigsburg, Hung Q. Le, John W. Ward, III | 2009-02-03 |
| 7475223 | Fetch-side instruction dispatch group formation | Brian R. Konigsburg, Hung Q. Le, John W. Ward, III | 2009-01-06 |
| 7426631 | Methods and systems for storing branch information in an address table of a processor | Brian R. Konigsburg, Wolfram Sauer, Samuel Thomas | 2008-09-16 |