Issued Patents All Time
Showing 25 most recent of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9999788 | Fast and accurate proton therapy dose calculations | Anne Elizabeth Gattiker, Damir A. Jamsek, Sani R. Nassif, Thomas H. Osiecki, Chin Ngai Sze +1 more | 2018-06-19 |
| 9946550 | Techniques for predicated execution in an out-of-order processor | Ram Rangan, Mark W. Stephenson, Lixin Zhang | 2018-04-17 |
| 9934079 | Fast remote communication and computation between processors using store and load operations on direct core-to-core memory | John B. Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani +1 more | 2018-04-03 |
| 9501285 | Register allocation to threads | Freeman Leigh Rawson, III, Lixin Zhang | 2016-11-22 |
| 9152569 | Non-uniform cache architecture (NUCA) | Jian Li, Ramakrishnan Rajamony, Xiaoxia Wu, Lixin Zhang | 2015-10-06 |
| 9026743 | Flexible replication with skewed mapping in multi-core chips | Jian Li | 2015-05-05 |
| 8966219 | Address translation through an intermediate address space | Ramakrishnan Rajamony, Lixin Zhang | 2015-02-24 |
| 8966187 | Flexible replication with skewed mapping in multi-core chips | Jian Li | 2015-02-24 |
| 8893148 | Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2014-11-18 |
| 8843705 | Read and write aware cache with a read portion and a write portion of a tag and status array | Jian Li, Ramakrishnan Rajamony, Lixin Zhang | 2014-09-23 |
| 8799625 | Fast remote communication and computation between processors using store and load operations on direct core-to-core memory | John B. Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani +1 more | 2014-08-05 |
| 8756608 | Method and system for performance isolation in virtualized environments | Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Lixin Zhang | 2014-06-17 |
| 8612687 | Latency-tolerant 3D on-chip memory organization | Jian Li, Lixin Zhang | 2013-12-17 |
| 8612691 | Assigning memory to on-chip coherence domains | Lixin Zhang | 2013-12-17 |
| 8595443 | Varying a data prefetch size based upon data usage | Ravi Kumar Arimilli, Gheorghe C. Cascaval, Balaram Sinharoy, Lixin Zhang | 2013-11-26 |
| 8589665 | Instruction set architecture extensions for performing power versus performance tradeoffs | John B. Carter, Jian Li, Karthick Rajamani, Lixin Zhang | 2013-11-19 |
| 8543769 | Fine grained cache allocation | Ramakrishnan Rajamony, Lixin Zhang | 2013-09-24 |
| 8543770 | Assigning memory to on-chip coherence domains | Lixin Zhang | 2013-09-24 |
| 8458408 | Cache directed sequential prefetch | Lixin Zhang | 2013-06-04 |
| 8358503 | Stackable module for energy-efficient computing systems | John B. Carter, Wael R. El-Essawy, Elmootazbellah Nabil Elnozahy, Wesley M. Felter, Madhusudan K. Iyengar +4 more | 2013-01-22 |
| 8346988 | Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units | Jian Li, Lixin Zhang | 2013-01-01 |
| 8341355 | Reducing energy consumption of set associative caches by reducing checked ways of the set association | Jian Li, Lixin Zhang | 2012-12-25 |
| 8312464 | Hardware based dynamic load balancing of message passing interface tasks by modifying tasks | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ramakrishnan Rajamony | 2012-11-13 |
| 8271729 | Read and write aware cache storing cache lines in a read-often portion and a write-often portion | Jian Li, Ramakrishnan Rajamony, Lixin Zhang | 2012-09-18 |
| 8266381 | Varying an amount of data retrieved from memory based upon an instruction hint | Ravi Kumar Arimilli, Gheorghe C. Cascaval, Balaram Sinharoy, Lixin Zhang | 2012-09-11 |