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USPTO Patent Rankings Data through Dec 31, 2025
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William E. Speight — 54 Patents

IBM: 54 patents #1,525 of 70,183Top 3%
Austin, TX: #395 of 18,064 inventorsTop 3%
Texas: #1,504 of 125,132 inventorsTop 2%
Overall (All Time): #46,969 of 4,157,543Top 2%
54 Patents All Time
William E. Speight has been granted 54 US patents while listed as an inventor at IBM. The first was granted in 2007 and the most recent in June 2018. William E. Speight ranks #46,969 of 4,157,543 US inventors in our database (top 1.1%). Patent records list William E. Speight in Austin, TX, US.

Issued Patents All Time

Showing 1–25 of 54 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9999788 Fast and accurate proton therapy dose calculations Anne Elizabeth Gattiker, Damir A. Jamsek, Sani R. Nassif, Thomas H. Osiecki, Chin Ngai Sze +1 more 2018-06-19 $3,279,000
9946550 Techniques for predicated execution in an out-of-order processor Ram Rangan, Mark W. Stephenson, Lixin Zhang 2018-04-17 $1,989,000
9934079 Fast remote communication and computation between processors using store and load operations on direct core-to-core memory John B. Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani +1 more 2018-04-03 $2,801,000
9501285 Register allocation to threads Freeman Leigh Rawson, III, Lixin Zhang 2016-11-22 $3,414,000
9152569 Non-uniform cache architecture (NUCA) Jian Li, Ramakrishnan Rajamony, Xiaoxia Wu, Lixin Zhang 2015-10-06 $5,963,000
9026743 Flexible replication with skewed mapping in multi-core chips Jian Li 2015-05-05 $8,777,000
8966219 Address translation through an intermediate address space Ramakrishnan Rajamony, Lixin Zhang 2015-02-24 $3,851,000
8966187 Flexible replication with skewed mapping in multi-core chips Jian Li 2015-02-24 $3,851,000
8893148 Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasks Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ramakrishnan Rajamony 2014-11-18 $3,249,000
8843705 Read and write aware cache with a read portion and a write portion of a tag and status array Jian Li, Ramakrishnan Rajamony, Lixin Zhang 2014-09-23 $6,171,000
8799625 Fast remote communication and computation between processors using store and load operations on direct core-to-core memory John B. Carter, Elmootazbellah Nabil Elnozahy, Ahmed Gheith, Eric Van Hansbergen, Karthick Rajamani +1 more 2014-08-05 $3,332,000
8756608 Method and system for performance isolation in virtualized environments Elmootazbellah Nabil Elnozahy, Ramakrishnan Rajamony, Lixin Zhang 2014-06-17 $4,121,000
8612687 Latency-tolerant 3D on-chip memory organization Jian Li, Lixin Zhang 2013-12-17 $6,242,000
8612691 Assigning memory to on-chip coherence domains Lixin Zhang 2013-12-17 $6,242,000
8595443 Varying a data prefetch size based upon data usage Ravi Kumar Arimilli, Gheorghe C. Cascaval, Balaram Sinharoy, Lixin Zhang 2013-11-26 $4,812,000
8589665 Instruction set architecture extensions for performing power versus performance tradeoffs John B. Carter, Jian Li, Karthick Rajamani, Lixin Zhang 2013-11-19 $3,686,000
8543769 Fine grained cache allocation Ramakrishnan Rajamony, Lixin Zhang 2013-09-24 $6,780,000
8543770 Assigning memory to on-chip coherence domains Lixin Zhang 2013-09-24 $6,780,000
8458408 Cache directed sequential prefetch Lixin Zhang 2013-06-04 $4,195,000
8358503 Stackable module for energy-efficient computing systems John B. Carter, Wael R. El-Essawy, Elmootazbellah Nabil Elnozahy, Wesley M. Felter, Madhusudan K. Iyengar +4 more 2013-01-22 $9,574,000
8346988 Techniques for dynamically sharing a fabric to facilitate off-chip communication for multiple on-chip units Jian Li, Lixin Zhang 2013-01-01
8341355 Reducing energy consumption of set associative caches by reducing checked ways of the set association Jian Li, Lixin Zhang 2012-12-25
8312464 Hardware based dynamic load balancing of message passing interface tasks by modifying tasks Lakshminarayana B. Arimilli, Ravi Kumar Arimilli, Ramakrishnan Rajamony 2012-11-13 $6,514,000
8271729 Read and write aware cache storing cache lines in a read-often portion and a write-often portion Jian Li, Ramakrishnan Rajamony, Lixin Zhang 2012-09-18 $5,189,000
8266381 Varying an amount of data retrieved from memory based upon an instruction hint Ravi Kumar Arimilli, Gheorghe C. Cascaval, Balaram Sinharoy, Lixin Zhang 2012-09-11 $6,476,000