Issued Patents All Time
Showing 51–73 of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7412620 | Method for testing ability to recover from cache directory errors | — | 2008-08-12 |
| 7269715 | Instruction grouping history on fetch-side dispatch group formation | Hung Q. Le, John W. Ward, III | 2007-09-11 |
| 7254700 | Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush | Brian W. Thompto | 2007-08-07 |
| 7120784 | Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment | Gregory W. Alexander, Scott Bruce Frommer, Balaram Sinharoy | 2006-10-10 |
| 7039768 | Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions | Gregory W. Alexander, Balaram Sinharoy | 2006-05-02 |
| 7032097 | Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache | Gregory W. Alexander, Balaram Sinharoy, William J. Starke | 2006-04-18 |
| 7000233 | Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread | Balaram Sinharoy | 2006-02-14 |
| 6662360 | Method and system for software control of hardware branch prediction mechanism in a data processor | Robert William Hay, James Allan Kahle, Brian R. Konigsburg, Balaram Sinharoy | 2003-12-09 |
| 6651162 | Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache | Shashank Nemawarkar, Balaram Sinharoy, William J. Starke | 2003-11-18 |
| 6484256 | Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table | Balaram Sinharoy | 2002-11-19 |
| 6385719 | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor | John Edward Derrick, Brian R. Konigsburg, Lee Evan Eisen | 2002-05-07 |
| 6304959 | Simplified method to generate BTAGs in a decode unit of a processing system | Brian R. Konigsburg, John Edward Derrick | 2001-10-16 |
| 6279105 | Pipelined two-cycle branch target address cache | Brian R. Konigsburg | 2001-08-21 |
| 5918044 | Apparatus and method for instruction fetching using a multi-port instruction cache directory | John Stephen Muhich | 1999-06-29 |
| 5894487 | Error detection of directory arrays in dynamic circuits | — | 1999-04-13 |
| 5872950 | Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages | John Stephen Muhich | 1999-02-16 |
| 5796998 | Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system | John Stephen Muhich, Adam R. Talcott, Steven Wayne White | 1998-08-18 |
| 5796758 | Self-checking content-addressable memory and method of operation for detecting multiple selected word lines | — | 1998-08-18 |
| 5765221 | Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register | Paul C. Rossbach, Chin-Cheng Kau | 1998-06-09 |
| 5758143 | Method for updating a branch history table in a processor which resolves multiple branches in a single cycle | — | 1998-05-26 |
| 5553255 | Data processor with programmable levels of speculative instruction fetching and method of operation | Danny K. Jain, Paul C. Rossbach | 1996-09-03 |
| 5421020 | Counter register implementation for speculative execution of branch on count instructions | — | 1995-05-30 |
| 5367703 | Method and system for enhanced branch history prediction accuracy in a superscalar processor system | — | 1994-11-22 |