Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8782584 | Post-placement cell shifting | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy +3 more | 2014-07-15 |
| 8578315 | Scheduling for parallel processing of regionally-constrained placement problem | Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi | 2013-11-05 |
| 8555221 | Partitioning for hardware-accelerated functional verification | Michael D. Moffitt, Matyas A. Sustik | 2013-10-08 |
| 8495534 | Post-placement cell shifting | Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Shyam Ramji, Lakshmi N Reddy +3 more | 2013-07-23 |
| 8370782 | Buffer-aware routing in integrated circuit design | Chuck ALPERT, Zhuo Li, Michael D. Moffitt, Chin Ngai Sze | 2013-02-05 |
| 8347257 | Detailed routability by cell placement | Charles J. Alpert, Andrew D. Huber, Zhuo Li, Gi-Joon Nam, Shyam Ramji +4 more | 2013-01-01 |
| 8327304 | Partitioning for hardware-accelerated functional verification | Michael D. Moffitt, Matyas A. Sustik | 2012-12-04 |
| 8245173 | Scheduling for parallel processing of regionally-constrained placement problem | Gi-Joon Nam, Shyam Ramji, Taraneh Taghavi | 2012-08-14 |
| 7996812 | Method of minimizing early-mode violations causing minimum impact to a chip design | Pooja M. Kotecha, Frank J. Musante, Veena S. Pureswaran, Louise H. Trevillyan | 2011-08-09 |
| 7882475 | Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors | Charles J. Alpert, Gi-Joon Nam, Haoxing Ren, Natarajan Viswanathan | 2011-02-01 |
| 7624366 | Clock aware placement | Charles J. Alpert, David J. Hathaway, William R. Migatz, Gi-Joon Nam, Haoxing Ren | 2009-11-24 |
| 7581201 | System and method for sign-off timing closure of a VLSI chip | Michael A. Kazda, Pooja M. Kotecha, Adam P. Matheny, Lakshmi N Reddy, Louise H. Trevillyan | 2009-08-25 |
| 7549137 | Latch placement for high performance and low power circuits | Charles J. Alpert, Shyam Ramji, Chin Ngai Sze | 2009-06-16 |
| 7467369 | Constrained detailed placement | Charles J. Alpert, Gi-Joon Nam, Haoxing Ren | 2008-12-16 |
| 7464356 | Method and apparatus for diffusion based cell placement migration | Charles J. Alpert, Haoxing Ren | 2008-12-09 |
| 7296252 | Clustering techniques for faster and better placement of VLSI circuits | Charles J. Alpert, Gi-Joon Nam, Sherief Reda | 2007-11-13 |
| 7089521 | Method for legalizing the placement of cells in an integrated circuit layout | Zahi M. Kurzum, Shyam Ramji | 2006-08-08 |
| 7076755 | Method for successive placement based refinement of a generalized cost function | Haoxing Ren, Zahi M. Kurzum, Shyam Ramji | 2006-07-11 |
| 7073144 | Stability metrics for placement to quantify the stability of placement algorithms | Charles J. Alpert, Gi-Joon Nam, Mehmet Can Yildiz | 2006-07-04 |
| 7047163 | Method and apparatus for applying fine-grained transforms during placement synthesis interaction | Kanad Chakraborty, Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy, Leon Stok +1 more | 2006-05-16 |
| 7020861 | Latch placement technique for reduced clock signal skew | Charles J. Alpert, Gary R. Ellis, Gi-Joon Nam | 2006-03-28 |
| 6996512 | Practical methodology for early buffer and wire resource allocation | Charles J. Alpert, Jiang Hu | 2006-02-07 |
| 6671867 | Analytical constraint generation for cut-based global placement | Charles J. Alpert, Gi-Joon Nam | 2003-12-30 |
| 6510540 | Windowing mechanism for reducing pessimism in cross-talk analysis of digital chips | Byron L. Krauter, Sharad Mehrotra, Jonathan Humphrey Saxman, David J. Widiger | 2003-01-21 |
| 6360350 | Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms | Carol Ivash Gabele, Stephen T. Quay, Parsotam T. Patel, Jean-Paul Watson | 2002-03-19 |