Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423499 | Resistance and capacitance aware preferred layer trimming | Derong Liu, Charles J. Alpert | 2025-09-23 |
| 12393760 | Wire density-aware layer assignment | Derong Liu, Wing-Kai Chow, Gracieli Posser, Charles J. Alpert | 2025-08-19 |
| 12393763 | Timing-based layer assignment | Derong Liu, Wing-Kai Chow, Charles J. Alpert | 2025-08-19 |
| 12314651 | Zigzag detection and handling for integrated circuit design | Hongxin Kong, Wing-Kai Chow | 2025-05-27 |
| 12216977 | Maximum turn constraint for routing of integrated circuit designs | Wing-Kai Chow, Hongxin Kong | 2025-02-04 |
| 11928500 | Multi-threaded network routing based on partitioning | Wing-Kai Chow | 2024-03-12 |
| 11734485 | Routing congestion based on fractional via cost and via density | Gracieli Posser, Derong Liu, Zhuo Li | 2023-08-22 |
| 11675955 | Routing using rule-based blockage extension | Derong Liu, Gracieli Posser, Zhuo Li | 2023-06-13 |
| 11461530 | Circuit design routing based on routing demand adjustment | Mateus Paiva Fogaça, Gracieli Posser, Wing-Kai Chow, Zhuo Li | 2022-10-04 |
| 11132489 | Layer assignment based on wirelength threshold | Derong Liu, Yi-Xiao Ding, Zhuo Li | 2021-09-28 |
| 11080457 | Layer assignment and routing based on resistance or capacitance characteristic | Derong Liu, Yi-Xiao Ding, Zhuo Li | 2021-08-03 |
| 11030377 | Routing based on pin placement within routing blockage | Wing-Kai Chow | 2021-06-08 |
| 11030378 | Track assignment by dynamic programming | Yi-Xiao Ding, Zhuo Li | 2021-06-08 |
| 10997352 | Routing congestion based on layer-assigned net and placement blockage | Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Zhuo Li, Derong Liu | 2021-05-04 |
| 10963617 | Modifying route topology to fix clock tree violations | Andrew Mark Chapman, William Robert Reece, Natarajan Viswanathan, Gracieli Posser, Zhuo Li | 2021-03-30 |
| 10885257 | Routing congestion based on via spacing and pin density | Gracieli Posser, Wing-Kai Chow, Zhuo Li | 2021-01-05 |
| 10755024 | System and method for routing in an integrated circuit design | Wing-Kai Chow, Zhuo Li | 2020-08-25 |
| 10706201 | Circuit design routing using multi-panel track assignment | Yi-Xiao Ding | 2020-07-07 |
| 10685164 | Circuit design routing based on parallel run length rules | Yi-Xiao Ding, Wing-Kai Chow, Gracieli Posser, Zhuo Li | 2020-06-16 |
| 10460063 | Integrated circuit routing based on enhanced topology | Wen-Hao Liu, Gracieli Posser, Wing-Kai Chow, Zhuo Li | 2019-10-29 |
| 10460066 | Routing framework to resolve single-entry constraint violations for integrated circuit designs | Gracieli Posser, Wen-Hao Liu, Wing-Kai Chow, Zhuo Li | 2019-10-29 |
| 10460065 | Routing topology generation using spine-like tree structure | Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Zhuo Li, Charles J. Alpert | 2019-10-29 |
| 10460064 | Partition-aware grid graph based hierarchical global routing | Gracieli Posser, Wen-Hao Liu, Zhuo Li | 2019-10-29 |
| 10289795 | Routing tree topology generation | Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Charles J. Alpert, Zhuo Li | 2019-05-14 |
| 10289792 | Systems and methods for clustering pins for power | Wing-Kai Chow, Wen-Hao Liu, Gracieli Posser | 2019-05-14 |