Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10534891 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Lakshmi N. Reddy | 2020-01-14 |
| 10528695 | Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation | Alexey Y. Lvov, Benjamin Neil Trombley, Myung-Chul Kim, Paul G. Villarrubia | 2020-01-07 |
| 10503841 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Jiang Hu | 2019-12-10 |
| 10496764 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Jiang Hu | 2019-12-03 |
| 10417375 | Time-driven placement and/or cloning of components for an integrated circuit | Woohyun Chung, Lakshmi N. Reddy | 2019-09-17 |
| 10372837 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Jiang Hu | 2019-08-06 |
| 10372836 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Jiang Hu | 2019-08-06 |
| 10354183 | Power-driven synthesis under latency constraints | Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha | 2019-07-16 |
| 10346558 | Integrated circuit buffering solutions considering sink delays | Ying Zhou, Stephen T. Quay, Lakshmi N. Reddy, Gustavo E. Tellez, Jiang Hu | 2019-07-09 |
| 10223496 | Triple and quad coloring shape layouts | Alexey Y. Lvov, Gustavo E. Tellez | 2019-03-05 |
| 10216882 | Critical path straightening system based on free-space aware and timing driven incremental placement | Jinwook Jung, Frank J. Musante, Shyam Ramji, Lakshmi N. Reddy, Gustavo E. Tellez +1 more | 2019-02-26 |
| 10102061 | Error checking and correction for NAND flash devices | Shawn P. Authement, Jente B. Kuang | 2018-10-16 |
| 9536600 | Simultaneous multi-page commands for non-volatile memories | Dongki Kim, Jente B. Kuang, Janani Mukundan | 2017-01-03 |
| 9524363 | Element placement in circuit design based on preferred location | Charles J. Alpert, Chin Ngai Sze, Paul G. Villarrubia, Natarajan Viswanathan | 2016-12-20 |
| 9417945 | Error checking and correction for NAND flash devices | Shawn P. Authement, Jente B. Kuang | 2016-08-16 |
| 9418190 | Virtual sub-net based routing | Sven Peyer, Ronald D. Rose, Sourav Saha | 2016-08-16 |
| 9298872 | Apportioning synthesis effort for better timing closure | Thomas E. Rosser, Manikandan Viswanath | 2016-03-29 |
| 9245084 | Virtual sub-net based routing | Sven Peyer, Ronald D. Rose, Sourav Saha | 2016-01-26 |
| 8954912 | Structured placement of latches/flip-flops to minimize clock power in high-performance designs | Charles J. Alpert, Zhuo Li, Shyam Ramji, Chin Ngai Sze, Paul G. Villarrubia +1 more | 2015-02-10 |
| 8930867 | Scheduling for parallel processing of regionally-constrained placement problem | Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia | 2015-01-06 |
| 8930873 | Creating regional routing blockages in integrated circuit design | Charles J. Alpert, Zhuo Li, Sven Peyer, Sourav Saha, Chin Ngai Sze +1 more | 2015-01-06 |
| 8909015 | Composition for high strength loose tube type fiber optic cable with excellent flexibility and impact resistance | Jeong Eun LIM, Yu-Hyoung Lee | 2014-12-09 |
| 8826215 | Routing centric design closure | Charles J. Alpert, Zhuo Li, Chin Ngai Sze, Paul G. Villarrubia | 2014-09-02 |
| 8782584 | Post-placement cell shifting | Charles J. Alpert, Zhuo Li, Shyam Ramji, Lakshmi N Reddy, Jarrod A. Roy +3 more | 2014-07-15 |
| 8769457 | Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design | Charles J. Alpert, Myung-Chul Kim, Shyam Ramji, Natarajan Viswanathan | 2014-07-01 |