Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8683411 | Electronic design automation object placement with partially region-constrained objects | Charles J. Alpert, John L. McCann, Shyam Ramji, Taraneh Taghavi, Natarajan Viswanathan | 2014-03-25 |
| 8677299 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Zhuo Li, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-18 |
| 8667441 | Clock optimization with local clock buffer control optimization | Charles J. Alpert, Zhuo Li, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2014-03-04 |
| 8635577 | Timing refinement re-routing | Michael A. Kazda, Zhuo Li, Ying Zhou | 2014-01-21 |
| 8595675 | Local objective optimization in global placement of an integrated circuit design | Charles J. Alpert, Myung-Chul Kim, Shyam Ramji, Natarajan Viswanathan | 2013-11-26 |
| 8578315 | Scheduling for parallel processing of regionally-constrained placement problem | Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia | 2013-11-05 |
| 8495548 | Multi-patterning lithography aware cell placement in integrated circuit design | Kanak B. Agarwal, Charles J. Alpert, Zhuo Li, Natarajan Viswanathan | 2013-07-23 |
| 8495534 | Post-placement cell shifting | Charles J. Alpert, Zhuo Li, Shyam Ramji, Lakshmi N Reddy, Jarrod A. Roy +3 more | 2013-07-23 |
| 8458634 | Latch clustering with proximity to local clock buffers | Charles J. Alpert, Zhuo Li, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan | 2013-06-04 |
| 8418108 | Accuracy pin-slew mode for gate delay calculation | Charles J. Alpert, Zhuo Li, David A. Papa, Chin Ngai Sze, Natarajan Viswanathan +1 more | 2013-04-09 |
| 8347257 | Detailed routability by cell placement | Charles J. Alpert, Andrew D. Huber, Zhuo Li, Shyam Ramji, Jarrod A. Roy +4 more | 2013-01-01 |
| 8347249 | Incremental timing optimization and placement | Charles J. Alpert, Zhuo Li, Shyam Ramji, Jarrod A. Roy, Natarajan Viswanathan | 2013-01-01 |
| 8245173 | Scheduling for parallel processing of regionally-constrained placement problem | Shyam Ramji, Taraneh Taghavi, Paul G. Villarrubia | 2012-08-14 |
| 8242358 | Micro coaxial cable for high bending performance | Chan-Yong Park, Il-Gun Seo, Jung Won Park, In-Ha Kim, Gun-Joo Lee +1 more | 2012-08-14 |
| 8198535 | Coaxial cable | Chan-Yong Park, Bong-Kwon Cho, Hyoung-Koog Lee, Jung Won Park, Dae Sung Lee | 2012-06-12 |
| 8108819 | Object placement in integrated circuit design | Charles J. Alpert, Jarrod A. Roy, Natarajan Vishvanathan | 2012-01-31 |
| 7934188 | Legalization of VLSI circuit placement with blockages using hierarchical row slicing | Charles J. Alpert, Michael W. Dotson, Shyam Ramji, Natarajan Viswanathan | 2011-04-26 |
| 7897874 | Foam coaxial cable and method for manufacturing the same | Chan-Yong Park, Bong-Kwon Cho, Jung Won Park, Dae Sung Lee | 2011-03-01 |
| 7882475 | Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors | Charles J. Alpert, Haoxing Ren, Paul G. Villarrubia, Natarajan Viswanathan | 2011-02-01 |
| 7624366 | Clock aware placement | Charles J. Alpert, David J. Hathaway, William R. Migatz, Haoxing Ren, Paul G. Villarrubia | 2009-11-24 |
| 7541542 | Micro coaxial cable | Chan-Yong Park, Jung Won Park, In-Ha Kim, June-Sun Kim, Il-Gun Seo +1 more | 2009-06-02 |
| 7507910 | Asymmetrical separator and communication cable having the same | Chan-Yong Park, Jong-Seb Baeck, Woo-Yong Dong | 2009-03-24 |
| 7467369 | Constrained detailed placement | Charles J. Alpert, Haoxing Ren, Paul G. Villarrubia | 2008-12-16 |
| 7399926 | Communication cable having outside spacer and method for producing the same | Chan-Yong Park, Jong-Seb Baeck, Woo-Yong Dong | 2008-07-15 |
| 7296252 | Clustering techniques for faster and better placement of VLSI circuits | Charles J. Alpert, Sherief Reda, Paul G. Villarrubia | 2007-11-13 |